Energy-filtered cold electron devices and methods

ABSTRACT

Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/115,999, filed Aug. 2, 2016, which is a U.S. national stageapplication under 35 U.S.C. § 371 of International Application No.PCT/US2015/014258, filed Feb. 3, 2015, which claims priority pursuant to35 U.S.C. § 119 to U.S. Provisional Patent Application Ser. No.61/935,493, filed Feb. 4, 2014, and U.S. Provisional Patent ApplicationSer. No. 62/032,554, filed Aug. 2, 2014, each of which is herebyincorporated by reference in its entirety.

FIELD OF INVENTION

The present invention relates generally to the field of electronics and,more particularly, to electronic devices and methods forultralow-power-dissipation electronics.

BACKGROUND ART

At finite temperatures, electrons in solids are thermally excited inaccordance with the Fermi-Dirac distribution. This electron thermalexcitation obscures or nullifies many novel and technologicallyimportant phenomena in various electron systems. For example, it canwipe out the Coulomb blockade in single-electron systems [1,2] anddeteriorate the efficiency of spin-valve effect in spintronic systems[3,4]. Electron thermal excitation can also significantly degrade theperformance of more mainstream electronic devices. For example, it isthe root cause of excessive power dissipation inmetal-oxide-semiconductor field-effect transistors (MOSFET); theelectron thermal excitation prevents a steep turning-on/off of electriccurrent, limiting the subthreshold swing to ˜60 mV/decade at roomtemperature, causing excessive power dissipation [5-7]. These are just afew examples, but the negative effect of electron thermal excitationprevails in solid-state electron systems in general. Therefore, if therewere a method that could enable manipulation of electron thermalexcitation, a broad range of scientific and technological benefits wouldbe expected.

Previous studies by others have demonstrated that it is possible tosuppress electron thermal excitations and obtain low electrontemperatures by utilizing discrete energy levels present in quantumdots. If electron transport is made to occur through a discrete energylevel, it can serve as an energy filter (or thermal filter) since onlythose electrons whose energies match the discrete energy level areallowed to participate in the transport. This has been experimentallydemonstrated using double quantum dot systems, in which the firstquantum dot adjacent to the source electrode serves as an energy filter,passing only cold electrons to the second quantum dot [8-10]. In asimilar manner, it has also been demonstrated that the discrete energylevels or superconducting energy gaps can be utilized for quantumcooling of electron gases through energy-selective electron tunneling[11-15]. Until now, studies have been focused on obtaining ultralowsub-Kelvin electrons and investigating their novel phenomena, while theentire system is cooled to cryogenic temperatures, typically less than 1K [8-15], regimes not suitable for practical applications.

SUMMARY OF THE INVENTION

This present invention provides new electronic devices, hereinafterreferred to as energy-filtered cold electron devices, which caneffectively suppress the Fermi-Dirac electron thermal excitation, lowerelectron temperature, decrease power dissipation by achieving anextremely small subthreshold swing of less than 10 mV/decade at roomtemperature which in turn reduces the supply voltage to less than 0.1V.A discrete energy state obtained in the quantum well serves as an energyfilter which can suppress the Fermi-Dirac smearing of electrons andhence effectively lower the electron temperature, leading to anextremely small subthreshold swing at room temperature. The presentinvention is primarily targeted at solving the problem of high powerdissipation and power consumption in electronic devices, which caneffectively increase the battery life of laptops, smart phones and otherelectronic gadgets. For military purposes, it is targeted at effectivelyreducing the weight of equipment carried by a soldier. This could mean a90% reduction in total weight of equipment that requires battery power.

The present invention demonstrates that cold electrons whose effectivetemperature is as low as ˜45 K can be created and transported at roomtemperature without any physical cooling using a structure having asequential arrangement of a source electrode, a quantum well (QW), aquantum dot (QD) and a drain electrode, in which a discrete state of theQW serves as an energy filter as electrons are transported from thesource to the drain. The key aspect of this approach is that onceelectrons are filtered by the QW state, they cannot gain energy becauseno path exists for electron excitation (except for the phononabsorption), and therefore, the electrons remain cold until transportedto the drain. This method holds promise for being used as a generalstrategy to raise the low-temperature operation regimes of variouselectron systems to room temperature or greatly enhance the performanceof electron systems at room temperature. This is demonstrated with twoexamples. First, cold electrons are used in single-electron transistors,in which energy-filtered cold electrons eliminate the need of thecooling liquid and produce Coulomb staircase and Coulomb oscillations atroom temperature. Second, the cold electrons enable an extremely steepcurrent turn-on/off capability of ˜10 mV/decade at room temperature, acritical advancement that would pave routes to the realization ofultralow-power-dissipation electronics.

The present invention provides an energy-filtered cold electron devicethat includes a first electrode disposed on an isolation layer, aninsulation layer disposed on the first electrode, a second electrodedisposed on the insulating layer, and a first tunneling barrierspontaneously formed or deposited on each outer surface of the firstelectrode and the second electrode. The first electrode, the insulatinglayer, the second electrode and the first tunneling barrier form a stackhaving an exposed insulating layer sidewalls and an exposed firsttunneling barrier sidewalls. Semiconductor or metal nanoparticles areattached on the exposed insulating layer sidewalls. A second tunnelingbarrier is formed from a dielectric material disposed between thesemiconductor or metal nanoparticles and the exposed first tunnelingbarrier sidewalls. Quantum wells or quantum dots are formed in theconduction band of the first tunneling barrier. Discrete energy levelsare formed in the quantum wells or quantum dots.

In addition, the present invention provides a method for fabricating anenergy-filtered cold electron device that includes the steps ofdepositing a first electrode on an isolation layer, depositing aninsulation layer on the first electrode, depositing a second electrodeon the insulating layer, and dispositing or spontaneously forming afirst tunneling barrier on each outer surface of the first electrode andthe second electrode. The first electrode, the insulating layer, thesecond electrode and the first tunneling barrier form a stack having anexposed insulating layer sidewalls and an exposed first tunnelingbarrier sidewalls. Additional steps include attaching semiconductor ormetal nanoparticles on the exposed insulating layer sidewalls, andforming a second tunneling barrier by depositing a dielectric materialbetween the semiconductor or metal nanoparticles and the exposed firsttunneling barrier sidewalls.

Moreover, the present invention provides an energy-filtered coldelectron nanopillar device that includes a first electrode disposed onan isolation layer, a first tunneling barrier disposed on the firstelectrode, a second tunneling barrier disposed on the first tunnelingbarrier, an island material comprised of a semiconductor or metaldisposed on the second tunneling barrier, an additional second tunnelingbarrier disposed on the island material, an additional first tunnelingbarrier disposed on the additional second tunneling barrier, and asecond electrode disposed on the additional first tunneling barrier. Thefirst electrode, the first tunneling barrier, the second tunnelingbarrier, the island material, the additional second tunneling barrier,the additional first tunneling barrier and the second electrode form ananopillar. Quantum wells or quantum dots are formed in the conductionbands of the first tunneling barrier and the additional first tunnelingbarrier. Discrete energy levels are forming in the quantum wells orquantum dots.

Furthermore, the present invention provides a method for fabricating anenergy-filtered cold electron nanopillar device that includes the stepsof depositing a first electrode on an isolation layer, depositing orspontaneously forming a first tunneling barrier on the first electrode,depositing a second tunneling barrier on the first tunneling barrier,depositing an island material on the second tunneling barrier,depositing an additional second tunneling barrier on the islandmaterial, depositing or spontaneously forming an additional firsttunneling barrier on the additional second tunneling barrier, depositinga second electrode on the additional first tunneling barrier, depositinga nanoparticle on the second electrode, producing a nanopillar using avertical etching process and the nanoparticle as an etching hard mask,and removing the nanoparticle.

The present invention also provides a device component that injectselectrons or holes having an electrode, a quantum well disposed adjacentto the electrode in which the energy level spacing of the quantum wellis at least 250 meV or larger, and a tunneling barrier disposed adjacentto the quantum well.

The device component that injects electrons or holes can be fabricatedby depositing an electrode on a substrate, forming a quantum welladjacent to the electrode, and forming a tunneling barrier adjacent tothe quantum well.

Similarly, the present invention provides a device component thatinjects electrons or holes having an electrode, a quantum dot disposedadjacent to the electrode in which the energy level spacing of thequantum dot is at least 250 meV or larger, and a tunneling barrierdisposed adjacent to the quantum dot.

The device component that injects electrons or holes can be fabricatedby depositing an electrode on a substrate, forming a quantum dotadjacent to the electrode, and forming a tunneling barrier adjacent tothe quantum dot.

The present invention provides a method for operating an energy-filteredcold electron transistor by providing the energy-filtered cold electrontransistor having a first electrode, a second electrode, a gateelectrode and an electron energy filter disposed between the firstelectrode and the second electrode, wherein the electron energy filtercomprises a quantum well, filtering out any thermally excited electronsusing the electron energy filter by a discrete state of the quantum wellat room temperature, transporting only energy-filtered cold electronsbetween the first and second electrodes, and controlling the transportof the energy-filtered cold electrons using the gate electrode.

In addition, the present invention provides an energy-filtered coldelectron transistor that includes a central island, a second tunnelingbarrier, an additional second tunneling barrier, a first tunnelingbarrier, an additional first tunneling barrier, a first electrode, asecond electrode, a gate dielectric and an a gate electrode. The centralisland is disposed on an isolation layer and has at least a first walland a second wall. The second tunneling barrier is disposed on the firstwall of the central island. The additional second tunneling barrier isdisposed on the second wall of the central island. The first tunnelingbarrier is disposed on the second tunneling barrier and a first portionof the isolation layer. The additional first tunneling barrier isdisposed on the additional second tunneling barrier and a second portionof the isolation layer. The first electrode is disposed on the firsttunneling barrier above the first portion of the isolation layer andadjacent to the first tunneling barrier disposed on the second tunnelingbarrier. The second electrode is disposed on the additional firsttunneling barrier above the second portion of the isolation layer andadjacent to the additional first tunneling barrier disposed on theadditional second tunneling barrier. The gate dielectric is disposedabove a portion of the first electrode, the first tunneling barrier, thesecond tunneling barrier, the central island, the additional secondtunneling barrier, the additional first tunneling barrier and a portionof the second electrode. Alternatively, the gate dielectric is disposedonly above the central island. The gate electrode is disposed on thegate dielectric.

Moreover, the present invention provides a method for forming anenergy-filtered cold electron transistor by providing a substrate,forming or depositing an isolation layer on the substrate, forming ordepositing a semiconductor material or a metal on the isolation layer,forming or depositing a sacrificial material on the semiconductormaterial or the metal, and forming a central island by etching orremoving the sacrificial material and the semiconductor material or themetal around the central island. A second tunneling barrier material isformed or deposited around the semiconductor material or the metal ofthe central island. The second tunneling barrier material forms a secondtunneling barrier on a first side of the central island and anadditional second tunneling barrier on a second side of the centralisland. A first tunneling barrier material is formed or deposited on topand around the sacrificial material on the central island, on the secondtunneling barrier, and on the isolation layer. The first tunnelingbarrier material forms a first tunneling barrier adjacent to the tosecond tunneling barrier and an additional first tunneling barrieradjacent to the additional second tunneling barrier. An electrodematerial is formed or deposited on the first tunneling barrier to form afirst electrode adjacent to the first tunneling barrier and a secondelectrode adjacent to the additional first tunneling barrier. Allmaterials above a plane substantially level with a top of the firstelectrode and the second electrode are removed or lifted off. A gatedielectric is formed or deposited above a portion of the firstelectrode, the first tunneling barrier, the second tunneling barrier,the central island, the additional second tunneling barrier, theadditional first tunneling barrier and a portion of the secondelectrode. Alternatively, a gate dielectric is formed or deposited onlyabove the central island. A gate electrode is formed or deposited on thegate dielectric.

The present invention is described in detail below with reference to theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and further advantages of the invention may be betterunderstood by referring to the following description in conjunction withthe accompanying drawings, in which:

FIGS. 1A-1C are schematics of electron energy filtering via electrontunneling through a quantum well state in accordance with one embodimentof the present invention;

FIGS. 2A-2C are graphs demonstrating energy-filtered cold electrontransport at room temperature in accordance with one embodiment of thepresent invention;

FIGS. 3A-3D are graphs showing the effectiveness of the energy filteringmanifested in narrow dI/dV peak widths at different temperatures inaccordance with one embodiment of the present invention;

FIG. 4 is a graph showing the I-V characteristics of a unit with ˜5.5 nmCdSe QD in accordance with one embodiment of the present invention;

FIGS. 5A-5B are graphs demonstrating effective temperature lowering inaccordance with one embodiment of the present invention;

FIGS. 6A-6B are energy diagrams for a DBTJ (double-barrier tunnelingjunction) for a zero voltage bias and a positive voltage bias,respectively, in accordance with one embodiment of the presentinvention;

FIG. 7 is a graph showing the I-V characteristics resulting from theFermi-Dirac thermal smearing in accordance with one embodiment of thepresent invention;

FIG. 8 is a graph showing the differential conductance, dI(V)/dV, thatresults from the Fermi-Dirac thermal smearing in accordance with oneembodiment of the present invention;

FIG. 9 is a graph showing the temperature dependence of the FWHMs (fullwidth at half maximum's) of the differential conductance peaks inaccordance with one embodiment of the present invention;

FIGS. 10A-10C show the modeling for energy-filtered cold electrontransport in accordance with one embodiment of the present invention;

FIGS. 11A-11C are graphs showing the functions used in the numericalcalculations in accordance with one embodiment of the present invention;

FIGS. 12A-12I are graphs showing the calculated results for the modelfor energy-filtered cold electron transport in accordance with oneembodiment of the present invention;

FIGS. 13A-13L show an application of energy-filtered cold electrontransport to single-electron transistors (SETs) in accordance with oneembodiment of the present invention;

FIG. 14 is a diagram showing the parameters that affect electron energyfiltering in accordance with one embodiment of the present invention;

FIGS. 15A-15B are diagrams and graphs showing the role of energy barrierE_(b) on the formation of a quantum well and its discrete state inaccordance with one embodiment of the present invention;

FIG. 16 is a flow chart for engineering the band bending usingself-assembled monolayers (SAMs) of dipolar molecules in accordance withone embodiment of the present invention;

FIGS. 17A-17C show an energy-filtered cold electron device structureusing vertical electrode configuration and a QD (semiconductornanoparticle) in accordance with one embodiment of the presentinvention;

FIG. 18 illustrates an energy-filtered cold electron device structurethat uses a nanopillar configuration in accordance with one embodimentof the present invention;

FIGS. 19A-19D illustrate the process for fabricating nanopillarstructures in accordance with one embodiment of the present invention;

FIGS. 20A-20D illustrate the process to make electrical contacts to thenanopillar in accordance with one embodiment of the present invention;

FIG. 21 is a top view and cross-section view of a schematic of anenergy-filtered cold electron transistor in accordance with oneembodiment of the present invention;

FIGS. 22A-22B are graphs showing the test of the gate design in FIG. 21with fabrication of single-electron transistors (SETs) in accordancewith one embodiment of the present invention;

FIGS. 23A-23B are graphs of the I-V characteristics demonstrating asteep current turning-on/off capability of ˜10 mV/decade at roomtemperature in accordance with one embodiment of the present invention;

FIGS. 24A-24B are schematics of a completed energy-filtered coldelectron nanopillar transistor with a gate electrode incorporated inaccordance with one embodiment of the present invention;

FIGS. 25A-25J illustrate the process flow for a gate insertion into thetwo-terminal energy-filtered cold electron nanopillar device(cross-sectional view) in accordance with one embodiment of the presentinvention;

FIGS. 26A-26C illustrate the large-scale fabrication of individuallyaddressable energy-filtered cold electron nanopillar transistors inaccordance with one embodiment of the present invention;

FIG. 27 is a schmatic of a metal-insulator-semiconductor (MIS) structurefor a direct measurement of the energy band bending of the Cr₂O₃ layerin accordance with one embodiment of the present invention;

FIGS. 28A-28B are graphs of the measured C-V characteristics for the MISunits with varying Cr₂O₃ layer thicknesses d_(Cr2O3) in accordance withone embodiment of the present invention;

FIG. 29 is a schematic of an example of energy-filtered cold electrontransistor that utilizes room-temperature energy filter in accordancewith one embodiment of the present invention;

FIGS. 30A-30J illustrates the process flow for fabricating theenergy-filtered cold electron transistor in FIG. 29 in accordance withone embodiment of the present invention;

FIGS. 31A-31B are a cross sectional view and top view of theenergy-filtered cold electron transistor in accordance with oneembodiment of the present invention; and

FIGS. 32A-32E are schematics of mask layouts used to fabricate theenergy-filtered cold electron transistor in FIG. 29 in accordance withone embodiment of the present invention.

DESCRIPTION OF THE INVENTION

While the making and using of various embodiments of the presentinvention are discussed in detail below, it should be appreciated thatthe present invention provides many applicable inventive concepts thatcan be embodied in a wide variety of specific contexts. The specificembodiments discussed herein are merely illustrative of specific ways tomake and use the invention and do not delimit the scope of theinvention.

Transistors that can operate with extremely low energy consumption wouldgenerate a lot of applications for military, commercial, and space use.For example, if the power consumption of battery-powered electronicdevices can be reduced by ˜100 times, without sacrificing theperformance, the battery weight of an instrument would be able to bereduced by ˜100 times. This would tremendously increase the capabilityof numerous military equipment, examples including unmanned aerialvehicles (UAVs), remote communication devices, remote sensing devices,missiles, submarines, aircrafts, and electronic devices that soldierscarry in the battlefield. Commercial applications are also expected tobe immense; for example, one may envision cell phones and laptops thatcan operate for a month without recharging.

The Fermi-Dirac (FD) distribution is a fundamental property that governsthe thermal behavior of electrons. At finite temperatures, it leads tothermal smearing of electrons around the Fermi level, which is generallyan undesirable effect that sets an intrinsic temperature limit forproper functioning of many electronic, optoelectronic, and spintronicsystems. Since the FD distribution cannot be subject to manipulation,the only way to suppress the FD smearing is to reduce the temperature.This intrinsic limitation requires many electronic/spintronic systems tobe cooled down to cryogenic temperatures (e.g. <77K) for properoperation, barring their implementations to practical applications. If,however, there exists a way to effectively suppress the FD smearing,many novel electronic/optoelectronic/spintronic systems would be able tooperate even at room temperature, leading to numerous military andcommercial applications.

The present invention provides a new method of manipulating thermalbehavior of electrons in such a way that the FD thermal smearing ofelectrons is effectively suppressed. The electrons are filtered by adiscrete energy level of a quantum well or quantum dot during electrontunneling so that only cold electrons are allowed to participate in thetunneling events. This energy-filtered electron tunneling effectivelysuppresses the FD thermal smearing or, equivalently, effectively lowersthe electron temperature without any physical cooling.

An important application of the energy-filtered electron tunneling is anew type of transistor “energy-filtered cold electron transistor” whichcan operate with extremely-low power consumption. The extremely largeheat generation (power consumption or power dissipation) of the currentstate-of-the-art transistors originates from the fact that, due tothermally excited electrons following the FD distribution, thetransistor cannot be abruptly turned off when voltage is reduced. Thepresent invention overcomes this limitation by filtering the thermallyexcited electrons and therefore effectively lowering the electrontemperature to 45K or below without any physical cooling (i.e., at roomtemperature), which means that transistors that can operate withextremely-low power dissipation.

Put another way, the key to decreasing the power consumption oftransistors is to reduce the subthreshold swing (SS), the measure of howfast a transistor can be turned off below the threshold voltage V_(th).With a low subthreshold swing, the supply voltage V_(DD) can be reducedand hence the power consumption (proportional to the square of V_(DD))while maintaining a low OFF-state current. For themetal-oxide-semiconductor-field-effect-transistor (MOSFET), however, theminimum possible subthreshold swing is 60 mV/decade at room temperature,and V_(DD) which is much smaller than one volt cannot be implementedwithout having a significant amount of OFF-state current. Since the 60mV/decade subthreshold swing for MOSFET is set by the thermodynamics(the Fermi-Dirac distribution of electrons), this is an intrinsic valuethat cannot be further reduced using prior art techniques. Althoughtunnel field-effect transistors (TFETs) in which interband tunneling isutilized have been actively investigated [7, 80], many challenges existfor TFETs, including controlling very abrupt doping profiles andimplementing low bandgap materials into Si platform.

The present invention demonstrates a new type of transistor, namedenergy-filtered cold electron transistor, which will have subthresholdswing of less than 10 mV/decade at room temperature. With this extremelysmall subthreshold swing, the supply voltage V_(DD) will be reduced toless than 0.1 V. The key element of this transistor is that its deviceconfiguration and materials selection produce an electron energy filter,which effectively suppresses the Fermi-Dirac distribution of electronsresulting in an effective electron temperature of 45K or less withoutany external cooling. Importantly, the energy-filtered cold electrontransistor can be fabricated with complete CMOS-compatible processes andmaterials, which will enable a facile implementation of theenergy-filtered cold electron transistors into the mainstreamsilicon-based IC platform.

As shown in FIG. 1A, the energy filtering structure of the presentinvention was created by incorporating a quantum well into adouble-barrier tunneling junction (DBTJ) configuration. When a voltagebias is applied to the usual DBTJ such that an energy level of thequantum dot ε_(D) is brought close to the Fermi level of the sourceelectrode, electrons can tunnel from the source to the QD, resulting ina current onset in the I-V characteristics as shown in FIG. 1A (bottom).At finite temperatures, however, this current onset is not abruptbecause thermally excited electrons in the source electrode can tunnelto the QD even if ε_(D) is positioned above μL (red arrow in FIG. 1A).This situation changes dramatically if a quantum well is insertedbetween the source and the tunneling barrier as shown in FIG. 1B. Inthis case, the electron transport from the quantum well energy levelε_(W) to the QD energy level ε_(D) can occur only if ε_(D) is equal toor lower than ε_(W) (red arrow in FIG. 1B)[16]. If ε_(D) is positionedabove ε_(W), the transport will be blocked since there is no availableexcitation path (except for the phonon absorption that can occur whenthe energy level offset is small, which will be discussed below). Thiswill produce an abrupt current step where the current onset correspondsto the alignment of ε_(W) and ε_(D) as shown in FIG. 1B (bottom).

The quantum well is formed between the source and the tunneling barrieron the source side (SiO₂) by using Cr as the source electrode, for whicha thin layer (˜2 nm) of Cr₂O₃ is naturally formed on the Cr surface andserves as the quantum well material as shown in FIG. 1B. Here theinterface dipoles and/or interface charges that spontaneously form atthe Cr₂O₃/SiO₂ interface [17-20] induce a band bending of the Cr₂O₃conduction band, producing the quantum well [21-25]. The discrete energystate in the quantum well serves as an energy filter for the injectionof electrons to the QD. This energy filtering effectively suppresses theFermi-Dirac (“FD”) smearing of electrons on the electrode, or,equivalently, effectively lowers the electron temperature, leading to anextremely small subthreshold swing, <10 mV/decade at room temperature.This energy filtering structure was fabricated in a three-dimensionalconfiguration shown in FIG. 1C using CMOS-compatible processes andmaterials. It is important to note that the fabrication of thisstructure does not require any elaborate procedures involved in forming2-D electron gases (2DEG) and creating QDs in the 2DEG, so that thefabrication can be carried out on a large scale using theCMOS-compatible processes and materials [26]. In this configuration, theelectrodes (Cr) are vertically separated by an insulating layer (SiO₂ orAl₂O₃), the QD is positioned at the sidewall of the insulating layer,and the SiO₂ between the QD and electrode serves as an additionaltunneling barrier. CdSe nanoparticles were used as QDs to investigatethe electron transport through their discrete energy states. The energylevel separation in the 2DEG QDs of prior art is much smaller than theroom-temperature thermal energy (˜25 meV), so that the energy-filteringdoes not work at room temperature for the prior art configurations andmaterials. In the present invention, the quantum well is formed in thethin tunneling barrier (˜2 nm), producing quantum well states whoseenergy separations are much larger than the room-temperature thermalenergy, enabling energy filtering at room temperature.

FIG. 2A shows the I-V characteristics measured at room temperature for aunit fabricated with the structure shown in FIG. 1C in which a ˜7.0 nmCdSe nanoparticle was used as the QD. Abrupt current jumps (indicated byarrows) are clearly resolved, which reveals that the energy filteringand subsequent cold electron transport work extremely well at roomtemperature. Each current jump corresponds to the alignment of an energylevel of the CdSe QD with the QW energy level ε_(W), where s, p, and drepresent the first three levels in the conduction band of the CdSe QDand h₁, h₂, and h₃ the first three levels in the valance band. A clearzero-conductance gap (˜2.2 V), which originates from the band gap of theCdSe QD, can also be seen.

For electron transport without the energy filtering, these abruptcurrent steps can be obtained only at low temperatures. FIG. 2B showsnumerically calculated I-Vs at varying temperatures in which theFermi-Dirac thermal excitation governs their temperature behavior. Theexperimental I-V in FIG. 2A can be achieved only when the temperature isbrought to ˜45 K (blue in FIG. 2B), where thermal excitation issufficiently suppressed. At room temperature, all the current steps arewiped out due to Fermi-Dirac thermal smearing (green in FIG. 2B). Notethat the I-Vs are vertically displaced by 30 nA for clarity.Experimentally, electron transport through a QD in the usual DBTJ wasextensively studied by others using scanning tunneling microscopy (STS)[27-31]. Note that their well-resolved current steps were observed onlyat low temperatures (<5 K), most often accompanied by non-thermalbroadening factors, such as optical phonon contributions [27-34]. Forexample, the I-V characteristics obtained for a CdSe QD showed that thebroadening A (definition in FIG. 1A) in the current steps is ˜50 mV at4.5 K [30]. On the other hand, the method in accordance with the presentinvention led to much more abrupt current steps even at roomtemperature: Δ is only ˜20 mV at 295 K (FIG. 2A).

To further investigate the abrupt current jumps in FIG. 2A, independentdirect differential conductance (dI/dV) measurements were carried outusing the lock-in technique at room temperature as shown in FIG. 2C (thedata in FIGS. 2A and 2C are from different units). The first three QDlevels in the conduction and valence band are labeled s, p, d and h₁,h₂, h₃, respectively. One observes well-resolved peaks, eachcorresponding to the current step (marked by the arrow) in the I-Vmeasurement in FIG. 2A. The peak widths in FIG. 2C are extremely narrow;the full widths at half maximum (FWHMs) of the peaks are only ˜18 meV.Were the usual Fermi-Dirac thermal smearing in effect, the same FWHMscould have been obtained only when the temperature were lowered to ˜45K, according to numerical calculation. In other words, the usual FDthermal smearing should have produced ˜100 mV FWHMs and the measurementin FIG. 2C demonstrates that a factor of >˜5 suppression of the FDsmearing has been obtained.

Temperature Dependence

To investigate the effect of temperature on the energy filtering,differential conductance measurements (using lock-in) were carried outat varying reservoir temperatures, ranging from 77K to 295K. FIG. 3Adisplays differential conductances obtained from a unit in which a ˜7 nmCdSe nanoparticle was used as the QD. The peak widths decrease as thetemperature is lowered; the FHWMs are ˜17, ˜10, ˜8 and ˜4 mV at 295,225, 150 and 77 K, respectively. At each temperature, the peak widthsare the same for all s, p and d peaks.

The small FWHMs and their temperature dependence in FIG. 3A will prevailwithout regard to any specific energy level of a QD since the energyfiltering occurs through an energy level of the QW, not the QD. Toverify this, a unit was fabricated having a ˜5.5 nm CdSe QD as itscentral island. Differential conductance measurements at varyingtemperatures are shown in FIG. 3B. Their peak positions well reflect thesize dependence of QD energy levels, in agreement with the literature[29, 35-39]; compared to the unit with ˜7 nm CdSe QD (FIG. 3A), the unitwith ˜5.5 nm CdSe QD shows a higher conduction band onset (at ˜1.3 V)and a larger s-p level separation (˜240 mV). Nevertheless, the peakwidths and their temperature dependence are essentially the same inFIGS. 3A and 3B, demonstrating that the same energy filtering process isin effect without regard to a specific QD energy level structure (seealso below).

Note that the peak widths in the differential conductance measurements,in FIGS. 3A-3B, are much narrower than those observed by others in STSmeasurements of QDs in the DBTJ configuration [27-34] (e.g., FWHMreaches as small as ˜3 meV at 77K). For the latter, the FWHMs aretypically larger than ˜50 mV even at cryogenic temperatures (<5 K). Forexample, a comparison in FIG. 3C shows that the peak from roomtemperature measurement in this invention (green) is much narrower thanthe one from an STS measurement of a CdSe QD at 4.9 K (red) [32].

For the experimental temperature range of 77K-295K, a linearrelationship was found between the FWHMs and the temperature, which isdisplayed in FIG. 3D (green). The temperature dependences of the FWHMswhich result from electron transport without the energy filtering arealso shown in FIG. 3D, one from calculations based on Fermi-Diracelectron energy distribution (blue line), which will be described below,and the other from reported STS measurements (red) [32]. Here note thatthe slope for the experimental STS data is almost the same as that fromthe Fermi-Dirac smearing calculations, affirming that the STS thermalbehavior is governed by the usual Fermi-Dirac smearing. Comparing allthree cases in FIG. 3D, it is clear that the present invention haseffectively filtered out hot electrons, leading to extremely narrow peakwidths over all temperature ranges explored (i.e., suppression of the FDsmearing by a factor of ˜6.5).

The temperature of electrons is determined by their energy distribution[11, 12], which is reflected on the dI/dV peak widths. One can,therefore, obtain effective electron temperatures of the energy-filteredelectrons by comparing the FWHMs of the experiment with those from theFermi-Dirac smearing calculations. For example, at reservoir temperatureof 295 K, the electron temperature becomes ˜45 K; in FIG. 3D, the FWHMfrom Fermi-Dirac electrons at 45 K is the same as the FWHM from theenergy-filtered electrons at reservoir temperature of 295 K. Likewise,electron temperatures of the energy-filtered electrons were obtained as˜35K, ˜22K and ˜10K for reservoir temperatures of 225K, 150K and 77K,respectively (see below). These cold electrons promise numerouspractical applications as will be discussed below.

As described above, FIG. 3B shows direct dI/dV measurements (using thelock-in technique) for a unit having a ˜5.5 nm CdSe QD. The I-Vmeasurements were also carried out for the same unit as shown in FIG. 4.The I-V shows clear current steps (indicated by the arrows), eachcorresponding to an alignment of the QW energy level ε_(W) with adiscrete energy level of the QD. Labels s, p and h₁, h₂ indicate thefirst two peaks in the conduction and valence band, respectively. Theseparation between the first two arrows in the positive bias (labeled sand p) is ˜237 meV. This value is the same as the s-p separation in thedI/dV measurements in FIG. 3B.

The factor of ˜6.5 suppression of the FD smearing (FIG. 3D) implies thatthe electron temperature can be effectively lowered by the same factor.This is demonstrated in FIGS. 5A-5B, in which the room-temperatureexperimental I-V is compared with simulations at room temperature (FIG.5A; the simulated I-V is vertically displaced by 20 nA for clarity) andat 45K (=295K/6.5) (FIG. 5B), respectively. Simulation carried out at295K (FIG. 5A) shows that the abrupt current changes and the currentplateaus no longer exist due to the FD smearing. On the other hand, whenthe effective temperature of 45K is used in the simulation, an excellentagreement between the experiment and the simulation is seen, FIG. 5B.This effective temperature lowering would have enormous practicalimplications since cryogenic temperatures (<45K) can be obtained withoutany physical cooling.

The calculation of the FWHMs for the Fermi-Dirac smearing in FIG. 3Dwill now be briefly described. FIGS. 6A and 6B are energy diagrams for aDBTJ for a zero voltage bias and a positive voltage bias, respectively.The lightly shaded areas in the electrodes schematically represent thethermal smearing at non-zero temperatures. When a voltage bias isapplied as in FIG. 6B, an electron with energy E (which may be differentfrom the source Fermi level μ_(S)) can tunnel into the QD if E alignswith the QD energy level α. For a bias voltage V, the voltage dropsacross the tunneling barrier 1 and 2 are ηV and (1−η)V, respectively,where η is the voltage division factor [30, 36] (η=C₂/(C₁+C₂), where C₁and C₂ are the junction capacitances for barrier 1 and barrier 2,respectively). For the usual DBTJ, first its I-V characteristics arecalculated that would result from the Fermi-Dirac distribution ofelectrons. Then the differential conductance dI/dV is obtained bynumerical differentiation of the I-V. The FWHM of the dI/dV peak isanalytically obtained. Consider the case in which there is no chargeaccumulation at the QD, i.e., consider the shell tunneling regime [30,51]. Since there is no charge accumulation Γ₁ is much smaller than Γ₂(Γ₁ and Γ₂: the tunneling rate through junction 1 and junction 2,respectively); once an electron tunnels from the source to the QD(through barrier 1), it tunnels out to the drain (through barrier 2)before the other electron from the source tunnels into the QD. Thecurrent is then determined by Γ₁ (the slower rate). Γ₁(E,V), theelectron tunneling rate from the source to the QD at electron energy Eand voltage bias V, is given by [52]

$\begin{matrix}{{\Gamma_{1}\left( {E,V} \right)} = {2\frac{2\pi}{\hslash}{\rho_{S}(E)}{\rho_{QD}\left( {E + {\eta\; e\; V}} \right)}{{T(E)}}^{2}{f(E)}}} & (1)\end{matrix}$where ρ_(S)(E) and ρ_(QD)(E) are the density of states for the sourceelectrode and the QD, respectively, f(E) is the Fermi-Dirac distributionfunction of the source with Fermi level at μ_(S), η is the voltagedivision factor and |T(E)|² is the tunneling transmission probability.The electrical current I(V) is obtained by integrating Γ₁(E,V) withrespect to E,

$\begin{matrix}{{I(V)} = {{e{\int_{0}^{\infty}{{\Gamma_{1}\left( {E,V} \right)}{dE}}}}\  = {\frac{4\;\pi\; e}{\hslash}{\int_{0}^{\infty}{{\rho_{S}(E)}{\rho_{QD}\left( {E + {\eta\;{eV}}} \right)}{{T(E)}}^{2}{f(E)}{dE}}}}}} & (2)\end{matrix}$where e is the charge of an electron. We simplify equation (2) byapproximating ρ_(S)(E) and T(E) with ρ_(S)(E_(F)) and T(E_(F)),respectively, where E_(F)(≈μ_(S)) is the Fermi energy of the sourceelectrode [52];

$\begin{matrix}{{I(V)} \cong {\frac{g_{0}}{e}{\int_{0}^{\infty}{{\rho_{QD}\left( {E + {\eta\;{eV}}} \right)}f(E){dE}}}}} & (3) \\{where} & \; \\{g_{0} = {\frac{4\;\pi\; e^{2}}{\hslash}{\rho_{S}\left( E_{F} \right)}{{T\left( E_{F} \right)}}^{2}}} & (4)\end{matrix}$

The discrete energy level of the QD is represented by ρ_(QD)(E) with thedelta function,ρ_(QD)(E)=δ(E−(E _(α)+μ_(S)))  (5)where E_(α) is the energy for the QD level α (with its reference energyat μ_(S); see FIG. 6A). From equations (3)-(5), we have

$\begin{matrix}{{{I(V)} \cong {\frac{g_{0}}{e}{f\left( {E_{\alpha} + \mu_{S} - {\eta\;{eV}}} \right)}}} = {\frac{g_{0}}{e}\frac{1}{e^{{({E_{\alpha} - {\eta\;{eV}}})}/{kT}} + 1}}} & (6)\end{matrix}$

Equation (6) indicates that with no electron accumulation at the QD theI-V is governed by the Fermi-Dirac distribution in the electrode. FIG. 7shows the I-V characteristics at 295 K. The I-V relationship fromequation (6) with the QD energy level E_(α) at 1.2 eV and T=295 K. Δ=˜90mV.

The differential conductance dI/dV is obtained from equation (6) as

$\begin{matrix}{\frac{{dI}(V)}{dV} = {\frac{\eta\; g_{0}}{kT}\frac{e^{{({E_{\alpha} - {\eta\;{eV}}})}/{kT}}}{\left\lbrack {e^{{({E_{\alpha} - {\eta\;{eV}}})}/{kT}} + 1} \right\rbrack^{2}}}} & (7)\end{matrix}$FIG. 8 shows the dI/dV relationship from equation (7). The maximum dI/dVis obtained when V=E_(α)/ηe,

$\begin{matrix}{\left( \frac{dI}{dV} \right)_{\max} = {\frac{{dI}(V)}{dV}{_{V = \frac{E_{\alpha}}{\eta\; e}}{= {\frac{1}{4}\frac{\eta\; g_{0}}{kT}}}}}} & (8)\end{matrix}$The voltages V_(HM) ⁺ and V_(HM) ⁻ are the bias voltages that give thehalf of the maximum differential conductance value (dI/dV)_(max) and canbe obtained from equations (7) and (8) and solving the followingequation,

$\begin{matrix}{{\frac{\eta\; g_{0}}{kT}\frac{e^{{({E_{\alpha} - {\eta\;{eV}}})}/{kT}}}{\left\lbrack {e^{{({E_{\alpha} - {\eta\;{eV}}})}/{kT}} + 1} \right\rbrack^{2}}} = {{\frac{1}{2}\left( \frac{dI}{dV} \right)_{\max}} = {\frac{1}{2}\left( {\frac{1}{4}\frac{\eta\; g_{0}}{kT}} \right)}}} & (9)\end{matrix}$By solving equation (9), we have

$\begin{matrix}{{V_{HM}^{+} = {\frac{E_{\alpha}}{\eta\; e} - {\frac{kT}{\eta\; e}{\ln\left( {3 - {2\sqrt{2}}} \right)}}}}{V_{HM}^{-} = {\frac{E_{\alpha}}{\eta\; e} - {\frac{kT}{\eta\; e}{\ln\left( {3 + {2\sqrt{2}}} \right)}}}}} & (10)\end{matrix}$The FWHM (in energy unit) is then

$\begin{matrix}\begin{matrix}{{FWHM} = {\eta\; e\;\left( {V_{HM}^{+} - V_{HM}^{-}} \right)}} \\{= {{kT}\left\lbrack {{\ln\left( {3 + {2\sqrt{2}}} \right)} - {\ln\left( {3 - {2\sqrt{2}}} \right)}} \right\rbrack}} \\{= {3.52549\;{{kT}.}}}\end{matrix} & (11)\end{matrix}$

When a voltage bias is applied between the source and the drain, thevoltage is divided across the barrier 1 and barrier 2. The voltagedivision factor η is defined such that the voltage drops across junction1 and junction 2 are ηV_(DS) and (1−η)V_(DS), respectively. One canobtain η from the following relationship [30, 35-36, 53-54]:ηeV _(zc) =E _(g) +U=E _(g,optical) +E _(e-h)  (12)where e is the charge of an electron, V_(zc) is the zero-conductance gap(voltage difference between the s peak (LUMO) and the h₁ peak (HOMO)) inthe I-V or dI/dV measurement, E_(g) is the bandgap of a QD [35, 37, 38](difference of the single-particle energy levels for LUMO (s) and HOMO(h₁)), U is the single-electron charging energy of the QD [30, 36, 53,55], E_(g,optical) is the optical bandgap [35, 37, 38, 56] and E_(e-h)is the electron-hole Coulomb interaction energy. The E_(e-h) is given by[27, 55, 57, 58]

$\begin{matrix}{E_{e - h} = \frac{1.79e^{2}}{4\;{\pi ɛ}_{0}ɛ_{in}R}} & (13)\end{matrix}$where ε₀ is the permittivity of free space, ε_(in) is the dielectricconstant of the QD (=8 for CdSe [30]) and R is the radius of the QD.From equations (12) and (13),

$\begin{matrix}{\eta = {{\left\lbrack {E_{g,{optical}} + \frac{1.79e^{2}}{4\;{\pi ɛ}_{0}ɛ_{in}R}} \right\rbrack/e}\; V_{zc}}} & (14)\end{matrix}$

From equation (14), one finds that the η's are 0.94 and 0.83 for unitsin FIGS. 3A and 3B, respectively. Table 1 summarizes the calculations:

TABLE 1 Voltage division factor η for the units in FIGS. 3A and 3B CdSeQD E_(g, optical) E_(e-h) V_(zc) Sample Diameter (nm) (eV) [56] (eV) (V)η Unit in FIG. 3A 7.0 1.937 0.092 2.169 0.94 Unit in FIG. 3B 5.5 2.0000.117 2.548 0.83For the unit in FIG. 3A, a differential conductance measurement gave thezero-conductance gap V_(ac) as 2.169 V. For the unit in FIG. 3B, the I-Vmeasurement gave the zero-conductance gap V_(zc) as 2.548 V (FIG. 4).The optical bandgaps E_(g,optical) were obtained from the reference 56using nominal CdSe QD sizes.

The differential conductance measurements in FIGS. 3A and 3B show thatthe peak widths decrease with decreasing temperatures. Their functionalrelationship is linear as detailed below.

Table 2 and 3 summarize the FWHMs of the measured differentialconductance peaks to in FIGS. 3A and 3B, respectively. FIG. 9 shows theFWHMs (in energy unit) as a function of temperature. The FWHMs at eachtemperature have very small deviations; at a given temperature, the FWHMvalues are very close to each other without regard to quantum dot levels(s, p or d) or the samples measured (the unit with 7.0 nm CdSe QD or theunit with 5.5 nm CdSe QD). A fit with the linear regression method showsthat the FWHM vs. temperature can be nicely described by a linearfunctional relationshipFWHM[meV]=0.0523×T−1.0715  (15)With an R² value as high as 0.944.

The effective temperature of the energy-filtered electrons can beobtained from Equations (11) and (15) asT _(eff)=[0.0523×T(bath temp.)−1.0715]/[3 0.52549×k]  (16)From equation (16), effective electron temperatures are 47 K, 35 K, 22 Kand 10 K when the reservoir temperatures are 295 K, 225 K, 150 K and 77K, respectively.

Table 2 shows the measured FWHMs at different temperatures for s, p andd peaks. η value of 0.94 (from Table 1) was used to obtain the FWHMs inenergy scale (meV).

TABLE 2 FWHMs of the differential conductance peaks (from the unit inFIG. 3A). s-peak p-peak d-peak FWHM FWHM FWHM FWHM FWHM FWHM Temperature(mV) (meV) (mV) (meV) (mV) (meV)  77 K 3.8 3.6 3.5 3.3 2.4 2.3 150 K 6.96.5 7.6 7.1 7.0 6.6 225 K 10.4 9.7 9.3 8.7 9.7 9.1 295 K 16.1 15.1 15.614.7 17.7 16.6

Table 3 shows the measured FWHMs at different temperatures for s and ppeaks. η value of 0.83 (from Table 1) was used to obtain the FWHMs inenergy scale (meV).

TABLE 3 FWHMs of the differential conductance peaks (from the unit inFIG. 3B) s-peak p-peak FWHM FWHM FWHM Temperature (mV) (meV) (mV) FWHM(meV)  77 K 4.3 3.6 4.3 3.6 150 K 8.4 7.0 9.4 7.8 225 K 10.7 8.9 12.210.2 295 K 18.9 15.7 16.9 14.0

A model for the energy-filtered cold electron transport of the presentinvention is shown in FIG. 10A-10C. The system is made of the followingcomponents, a source electrode (L), a quantum well (QW), a quantum dot(QD) and a drain electrode (R), with tunneling barriers separating them.Tunneling barrier on the source side separates the QW and the QD, andtunneling barrier on the drain side separates the QD and the drain (R).Electrons tunnel between the adjacent components in a sequential manner.The QW on the drain side does not contribute to the energy filteringsince under the condition ε_(D)>μ_(R), electrons in the QD will tunnelout to the drain anyway without regard to the presence of QW in thedrain side. For simplicity, the model does not include the QW on thedrain side.

The tunneling rates between the adjacent components are defined as Γ_(L)^(±)(i_(W)), Γ_(D) ^(±)(i_(W)), Γ_(W) ^(±)(i_(D)) and Γ_(R) ^(±)(i_(D)).Γ_(L) ^(±)(i_(W)) is the tunneling rate when the number of electrons inthe QW before the tunneling is i_(W), where the superscript “+” and “−”represents an electron is added to the QW and subtracted from the QW,respectively, and the subscript “L” represents the electron addition andsubtraction is through the source electrode (L). Other rates are definedwith the same manner as follows. TAW is the rate for an electron totunnel from the QD to the QW (“+”) or from QW to QD (“−”) when thenumber of electrons in the QW before tunneling is i_(W). Γ_(W)^(±)(i_(D)) is the rate for an electron to tunnel from the QW to the QD(“+”) or from QD to QW (“−”) when the number of electrons in the QDlevel before tunneling is i_(D). Γ_(R) ^(±)(i_(D)) is the rate for anelectron to tunnel from the drain electrode (R) to the QD (“+”) or fromQD to R (“−”) when the number of electrons in the QD before thetransport is i_(D). These rates are governed by the positions ofchemical potentials/energy levels μ_(L), ε_(W), ε_(D) and μ_(R) of thesource, QW, QD and drain, respectively. For a given set of rates, therate equations are simultaneously solved [28], which gives an electricalcurrent I at a voltage bias V (i.e., the I-V). The I-V's anddifferential conductances (dI/dV's) from the model calculations are ingood agreement with the experimental data over all temperature rangesinvestigated (77 K-295 K).

For the electron tunneling between the QW and the QD, inelastic electrontunneling processes are included. Referring to FIG. 10B, it is assumedthat an electron tunneling from a lower energy state to a higher energystate (energy gain) is possible if coupled with a phonon absorption [41,42]. The tunneling probability of the inelastic tunneling through phononabsorption Γ_(absorp)(ε, T) is given by [41]Γ_(absorp)(ε,T)=n(|ε|,T)A(|ε|)  (17)where ε<0 (we define ε<0 for the energy gain), n(|ε|, T) is theBose-Einstein distribution function of phonon population, n(ε(>0),T)=1/(e^(ε/kT)−1), where T is the absolute temperature and k is theBoltzmann constant and A(ε) is the Einstein A coefficient forspontaneous emission of phonons [41, 42]. The total tunnelingprobability includes the contribution by the elastic tunnelingΓ_(elastic)(ε), for which the lifetime broadening with the Lorentziandistribution [10, 24, 46, 59] is assumed and is given by

$\begin{matrix}{{\gamma_{elastic}(ɛ)} = {\frac{2}{\hslash}\left( \frac{\hslash\; T_{elastic}}{2} \right)^{2}\frac{\frac{\hslash\; T_{elastic}}{2}}{ɛ^{2} + \left( \frac{\hslash\; T_{elastic}}{2} \right)^{2}}}} & (18)\end{matrix}$where

is the reduced Planck constant and T_(elastic) is the elastic tunnelingprobability when the QW energy level and QD energy level align exactly(i.e., when ε=0). The total tunneling probability Γ(ε<0, T) is then

$\begin{matrix}\begin{matrix}{{\gamma\left( {{ɛ < 0},T} \right)} = {{\gamma_{absorp}\left( {ɛ,T} \right)} + {\gamma_{elastic}(ɛ)}}} \\{= {{{n\left( {{ɛ},T} \right)}{A\left( {ɛ} \right)}} + {\gamma_{elastic}(ɛ)}}} \\{= {{{n\left( {{ɛ},T} \right)}{A\left( {ɛ} \right)}} + {\frac{2}{\overset{\_}{h}}\left( \frac{\hslash\; T_{elastic}}{2} \right)^{2}}}} \\{\frac{\frac{\hslash\; T_{elastic}}{2}}{ɛ^{2} + \left( \frac{\overset{\_}{h}T_{elastic}}{2} \right)^{2}}} \\{= {{{1/\left( {e^{{ɛ}/{kT}} - 1} \right)}{A\left( {ɛ} \right)}} + {\frac{2}{h}\left( \frac{\hslash\; T_{elastic}}{2} \right)^{2}}}} \\{\frac{\frac{\hslash\; T_{elastic}}{2}}{ɛ^{2} + \left( \frac{\hslash\; T_{elastic}}{2} \right)^{2}}}\end{matrix} & \begin{matrix}\begin{matrix}\begin{matrix}\begin{matrix}\begin{matrix}(19) \\\;\end{matrix} \\\;\end{matrix} \\\;\end{matrix} \\\;\end{matrix} \\\begin{matrix}\begin{matrix}\begin{matrix}\; \\\;\end{matrix} \\\;\end{matrix} \\(20)\end{matrix}\end{matrix}\end{matrix}$

Referring to FIG. 10C, an inelastic tunneling from a higher energy stateto a lower energy state (energy loss) occurs through phonon emission[10, 41, 42] and other energy relaxation processes [16, 24, 43-45](e.g., interface-roughness scattering, impurity scattering, alloydisorder scattering), which are represented by Γ_(emiss)(ε,T) andΓ_(relax)(ε), respectively. The tunneling probability through phononemission Γ_(emiss)(ε, T) is given by [41, 42]

$\begin{matrix}\begin{matrix}{{\gamma_{emiss}\left( {ɛ,T} \right)} = {\left\lbrack {{n\left( {ɛ,T} \right)} + 1} \right\rbrack{A(ɛ)}}} \\{= {\left\lbrack {{1/\left( {e^{ɛ/{kT}} - 1} \right)} + 1} \right\rbrack{A(ɛ)}}}\end{matrix} & (21)\end{matrix}$

The total tunneling probability in which an electron loses the energy inthe tunneling (ε>0) is then

$\begin{matrix}\begin{matrix}{{\gamma\left( {{ɛ > 0},T} \right)} = {{\gamma_{emiss}\left( {ɛ,T} \right)} + {\gamma_{elastic}(ɛ)} + {\gamma_{relax}(ɛ)}}} \\{= {{\left\lbrack {{n\left( {ɛ,T} \right)} + 1} \right\rbrack{A(ɛ)}} + {\gamma_{relax}(ɛ)} + {\gamma_{elastic}(ɛ)}}} \\{= {{\left\lbrack {{1/\left( {e^{ɛ/{kT}} - 1} \right)} + 1} \right\rbrack{A(ɛ)}} + {\frac{2}{\hslash\;}\left( \frac{\hslash\; T_{elastic}}{2} \right)^{2}}}} \\{\frac{\frac{\hslash\; T_{elastic}}{2}}{ɛ^{2} + \left( \frac{\hslash\; T_{elastic}}{2} \right)^{2}} + {\gamma_{relax}(ɛ)}}\end{matrix} & \begin{matrix}\begin{matrix}\begin{matrix}\begin{matrix}\begin{matrix}\begin{matrix}(22) \\\;\end{matrix} \\\;\end{matrix} \\\;\end{matrix} \\\;\end{matrix} \\(23)\end{matrix} \\\;\end{matrix}\end{matrix}$

Note that Γ(ε<0, T) and γ(ε>0, T) are temperature dependent through theBose-Einstein distribution function, which is the origin of thetemperature dependence of the I-V's and dI/dV's. The tunnelingprobabilities Γ(ε<0, T) and Γ(ε>0, T), along with the probabilities ofelectrons occupying the QW and QD states, determine the tunneling ratesΓ_(D) ^(±)(i_(W)) and Γ_(W) ^(±)(i_(D)).

The rate equations are constructed as follows. Define P_(W)(i_(W)) asthe probability that i_(W) number of electrons reside in the QW, wherei_(W) can be either 0, 1 or 2. Similarly, P_(D)(i_(D)) is theprobability that i_(D) number of electrons reside in the QD, where i_(D)can be either 0 or 1 (since the single-electron charging energy of ourQD is significant, ˜100 meV, the state having two electrons in the QDlevel is treated as a different state having a higher energy). Then, thetunneling rates Γ_(L) ^(±)(i_(W)), Γ_(D) ^(±)(i_(W)), Γ_(W) ^(±)(i_(D))and Γ_(R) ^(±)(i_(D)) are related to the tunneling probabilities Γ(ε<0,T) and γ(ε>0, T) and the occupation probabilities P_(W)(i_(W)) andP_(D)(i_(D)) as follows:Γ_(L) ⁺(0)=f _(L)(ε_(W))×D _(L)(ε_(W))×T _(L)  (24)Γ_(L) ⁺(1)=f _(L)(ε_(W))×D _(L)(ε_(W))×T _(L)  (25)Γ_(L) ⁻(1)=[1−f _(L)(ε_(W))]×D _(L)(ε_(W))×T _(L)  (26)Γ_(L) ⁻(2)=[1−f _(L)(ε_(W))]×D _(L)(ε_(W))×T _(L)  (27)Γ_(D) ⁺(0)=γ(ε_(D)−ε_(W) ,T)×P _(D)(1)  (28)Γ_(D) ⁺(1)=γ(ε_(D)−ε_(W) ,T)×P _(D)(1)  (29)Γ_(D) ⁻(1)=γ(ε_(W)−ε_(D) ,T)×P _(D)(0)  (30)Γ_(D) ⁻(2)=γ(ε_(W)−ε_(D) ,T)×P _(D)(0)  (31)Γ_(W) ⁺(0)=γ(ε_(W)−ε_(D) ,T)×[P _(W)(1)+P _(W)(2)]  (32)Γ_(W) ⁻(1)=γ(ε_(D)−ε_(W) ,T)×[P _(W)(0)+P _(W)(1)]  (33)Γ_(R) ⁺(0)=f _(R)(ε_(D))×D _(R)(ε_(D))×T _(R)  (34)Γ_(R) ⁻(1)=[1−f _(R)(ε_(D))]×D _(R)(ε_(D))×T _(R)  (35)where f_(L)(E) and f_(L)(E) are the Fermi-Dirac functions with chemicalpotential μ_(L) and μ_(R) for source (L) and drain (R) electrode,respectively, ε_(W) and ε_(D) are the energies of the QW and the QDstates, respectively, T_(L) is the tunneling probability for electrontunneling between the source (L) and the QW, T_(R) is the tunnelingprobability for electron tunneling between the QD and the drain (R),D_(L)(E) and D_(R)(E) are the density of states for the source and thedrain electrodes, respectively. As shown in equations (24)-(35), thetunneling rates Γ_(L) ^(±)(i_(W)), Γ_(D) ^(±)(i_(W)), Γ_(W) ^(±)(i_(D))and Γ_(R) ^(±)(i_(D)) are determined by the positions of μ_(L), ε_(W),ε_(D) and μ_(R), which in turn are determined by the voltage bias Vapplied between the source and the drain. Their relationships areμ_(L)−μ_(R)=eV, Δ(ε_(W)−ε_(D))=ηeV and Δ(ε_(D)−μ_(R))=(1−η)eV.

At steady state, the transition rates between two adjacentconfigurations are the same (the net transition is zero). For two QWconfigurations with i_(W)=0 and i_(W)=1, for example, the transitionrates between the two are the same:P _(W)(0)×[Γ_(L) ⁺(0)+Γ_(D) ⁺(0)]=P _(W)(1)×[Γ_(L) ⁻(1)+Γ_(D)⁻(1)]  (36)Likewise, the transition rates between two QW configurations withi_(W)=1 and i_(W)=2 are the same, which gives:P _(W)(1)×[Γ_(L) ⁺(1)+Γ_(D) ⁺(1)]=P _(W)(2)×[Γ_(L) ⁻(2)+Γ_(D)⁻(2)]  (37)Similarly, the transition rates between two adjacent QD configurationsare the same:P _(D)(0)×[Γ_(W) ⁺(0)+Γ_(R) ⁺(0)]=P _(D)(1)×[Γ_(W) ⁻(1)+Γ_(R)⁻(1)]  (38)

One also has the following equations since the sum of the probabilitiesshould be unity:P _(W)(0)+P _(W)(1)+P _(W)(2)=1  (39)and P _(D)(0)+P _(D)(1)=1  (40)

Since there are five equations, (36)-(40), and five unknowns, P_(W)(0),P_(W)(1), P_(W)(2), P_(D)(0) and P_(D)(1), the simultaneous equationscan be solved. For a given set of tunneling rates Γ_(L) ^(±)(i_(W)),Γ_(D) ^(±)(i_(W)), Γ_(W) ⁺(i_(D)) and Γ_(R) ^(±)(i_(W)) for a specificV, one numerically solves the simultaneous equations (36)-(40) andobtain P_(W)(0), P_(W)(1), P_(W)(2), P_(D)(0) and P_(D)(1). Theelectrical current I is then given byI(V)=e×[P _(D)(1)×Γ_(R) ⁻(1)−P _(D)(0)×Γ_(R) ⁺(0)]  (41)where e is the charge of an electron. The dI/dV is obtained by numericaldifferentiation of the I(V).

Numerical calculations were carried out using the model above. Forfunctions A(ε), γ_(relax)(ε) and γ_(elastic) (ε) in equations (17)-(23),the functional forms shown in FIGS. 11A-11C [24, 41, 42, 46, 59] wereused. The other parameters used were: T_(L)×D_(L)(ε_(W))=1.3×10¹¹[1/sec] and T_(R)×D_(R)(ε_(D))=1.3×10¹¹ [1/sec], where constant valuesof T_(L), T_(R), D_(L) and D_(R) were assumed. μ_(L)=0 (reference energyzero), ε_(W)=0, ε_(D)=E_(S)−ηeV (where E_(S) is the position of thes-level at V=0; V_(S)=E_(S)/ηe) and μ_(R)=−eV.

Equations (36)-(40) were numerically solved and the I(V) was obtained.FIGS. 12A-12H show resulting I-V and dI/dV calculations at differenttemperatures. An abrupt current jump, Δ32˜15 mV, is found at roomtemperature, FIG. 12A, in good agreement with the experimentalmeasurement in FIG. 2A. The current jumps become more abrupt as thetemperature decreases, FIGS. 12B-12D. The dI/dV's, FIGS. 12E-12H, shownarrow peak widths, with the peak width decreasing with decreasingtemperature, in good agreement with the differential conductancemeasurements in FIGS. 3A-3B. Note that the dI/dV peaks in FIGS. 3A-3Bare of a triangular shape, not Gaussian or Lorentzian. The modelcalculations in FIG. 12E-12H faithfully reproduce the triangular-typedI/dV peaks. For quantitative comparisons, the FWHMs from the modelcalculations and those from the experimental measurements are displayedin FIG. 12I. A very good agreement is found between them over thetemperature range investigated (77K-295K).

The electron energy filtering and its associated cold electron transporthave profound technical implications. Various electron systems/devicesthat have so far been able to function only at low temperatures couldnow be made to work at higher temperatures, in particular, at roomtemperature. Also, for many electronic devices that operate at roomtemperature, the cold electrons could be used to greatly enhance theirperformances. Two examples will now be presented. First, the use of coldelectrons in single-electron transistors (SETs) will be demonstrated,which results in clear Coulomb staircase and Coulomb oscillations atroom temperature without external cooling. Second, it will be shown thatcold electron transport can lead to an extremely steep currentturn-on/off capability, in which a voltage change of only ˜10 mV enablesa 10 fold current change (˜10 mV/decade) at room temperature.

Single-electron transistors (SETs) were fabricated using theconfiguration shown in FIG. 1C, but with two alterations: 1) the CdSe QDwas replaced by a metal nanoparticle (˜10 nm Au nanoparticle), and 2) agate electrode was added using the configuration reported previously, inwhich the gate encompasses the periphery of the drain/insulatinglayer/source stack in FIG. 1C [26]. FIGS. 13A-13L show the applicationof energy-filtered cold electron transport to SETs. FIG. 13A shows themeasured I-V characteristics of a fabricated SET at differenttemperatures. The Coulomb staircase is clearly seen at all temperatures,including room temperature. Above 10 K, each I-V is vertically displacedby 75 pA from the lower temperature one for clarity. V_(DS):source-drain voltage. I_(DS): source-drain current. FIG. 13B shows theI-V characteristics calculated with orthodox theory under the usualFermi-Dirac distribution (Simulator: SIMON 2.0). FIG. 13C shows themeasured Coulomb oscillations at different temperatures. V_(G): gatevoltage. V_(DS) was 10 mV. Above 10 K, each I-V is vertically displacedby 15 pA from the lower temperature one for clarity. FIG. 13D shows theCoulomb oscillations calculated with orthodox theory under the usualFermi-Dirac distribution. All temperatures indicated in FIGS. 13A-13Dare the reservoir temperatures. FIGS. 13E-13F show a comparison of theexperimental and simulated Coulomb staircases (FIG. 13E) and Coulomboscillations (FIG. 13F) at 10 K. T(exp): the reservoir temperature atwhich the experiment was carried out. T(sim): the simulationtemperature. FIGS. 13G-13L show a comparison of experimental andsimulated Coulomb staircases and Coulomb oscillations at elevatedreservoir temperatures (100 K-295 K). For the simulations, the effectiveelectron temperatures were used in the orthodox theory calculation. Justa single set of parameters (except for the background charge Q₀ [40])was used for all simulations in FIGS. 13B, 13D and 13E-13L. Theparameters are C₁=0.85 aF, C₂=2.9 aF, C_(G)=0.52 aF, R₁=8.7×10⁷Ω andR₂=6.6×10⁸Ω. The background charges Q₀ for FIGS. 13E-13L are −0.075e,0.45e, 0.075e, 0.40e, −0.075e, 0.50e, −0.025e and 0.50e, respectively.

FIGS. 13A and 13C display measured I-V characteristics of a fabricatedSET at different temperatures. Over all temperatures studied, includingroom temperature, clear single-electron transport behavior, i.e.,Coulomb staircases (FIG. 13A) and Coulomb oscillations (FIG. 13C), isobserved. The temperature behavior observed here well reflects theeffectiveness of our method as follows. At the lowest temperature (10 K)the Coulomb staircase and Coulomb oscillations are accurately describedby the orthodox theory of single-electron transport [40, 47] asevidenced by the excellent match between the experiment (blue dots) andthe theory (red lines) in FIGS. 13E and 13F. Note that the suppressed FDsmearing has a profound effect on the SET. As shown in FIGS. 13A and13C, these low-temperature (10 K) SET characteristics are well preservedeven at much higher temperatures (100-295 K). That is, raising thetemperature makes only a minor change on the SET characteristics,dramatically increasing the operation temperature range of SETs. Furtheranalysis shows that the effective temperature lowering explains all theexperimental observations in FIGS. 13A and 13C extremely well. Note thatwith the usual Fermi-Dirac thermal smearing in effect (i.e., no energyfiltering), the Coulomb staircases and Coulomb oscillations aresubstantially or completely wiped out at these temperatures, FIGS. 13Band 13D.

The preservation of the Coulomb staircases and Coulomb oscillations atelevated reservoir temperatures is explained by the fact that theenergy-filtered electrons are much colder than the reservoir.Quantitative analysis can be made using the effective temperatures ofthe energy-filtered electrons. As discussed earlier, by comparing theFWHMs in FIG. 3D (see equation (16)), one gets effective electrontemperatures ˜45 K, ˜30 K and ˜15 K for the reservoir temperatures 295K, 200 K and 100 K, respectively. These low electron temperaturesexplain the experimental data in FIGS. 13A and 13C extremely well. Thisis shown in FIGS. 13G-13L, in which the orthodox theory calculations(red lines) at these low temperatures faithfully reproduce all theexperimental Coulomb staircase and Coulomb oscillation data (dots). Thebenefit of having low-temperature electrons is clearly seen in thecurrent SET example: the requirement for cooling with liquid He/N₂ canbe lifted, yet the low-temperature SET performance remains. With similarmethodology, it is highly probable that the same benefit can be extendedto other systems, such as spintronic and optoelectronic devices.

The second example is related to obtaining a steep current turn-on/offcapability for field-effect transistors, a critical element forrealizing ultralow-power-dissipation electronics. Thermodynamics imposesa fundamental limit on the steepness of current turn-on/off as ln10·(kT/e). Its value at room temperature is 60 mV/decade, which limitsvoltage scaling and reduction of power dissipation [6]. For a solution,studies have been carried out in search of new types of transistors thatdo not rely on electron thermal injection, for example, the tunnelfield-effect transistor (TFET) which uses band-to-band tunneling [6].Many experimental challenges, however, have limited progress and to ourbest knowledge, the most steep experimental turn-on/off value reportedis ˜40 mV/decade over about one order of magnitude of drain current [6,48-50]. In contrast, the low electron temperature of the presentinvention provides a simple route to extremely steep current turn-on/offoperation: at room temperature (reservoir), the electron temperature of45 K leads to a current turn-on/off steepness of 9 mV/decade, from ln10·(k·45/e). Its experimental confirmation is displayed in FIGS.23A-23B, where a steepness of ˜10 mV/decade is demonstrated. The presentvalue of ˜10 mV/decade can lead to approximately 2 orders of magnitudereduction in power dissipation compared to the currently most advancedCMOS transistors, paving a new route toward ultralow-power-dissipationelectronics.

As previously described, our invention enables effective suppression ofthe FD thermal smearing and lowering electron temperatures by a factorof ˜6.5. Although the factor of ˜6.5 is already a very significantnumber, the foregoing discussion describes key factors to furthersuppress the FD smearing and reduce electron temperatures even further.

As outlined in FIG. 1B, the energy filtering process requires a discretestate which is spatially located between the electrode and the tunnelingbarrier. This discrete energy state is obtained by creating a quantumwell between the electrode and the tunneling barrier. This isaccomplished through a proper selection of materials, their nanoscalegeometric arrangement, and engineering the energy band bending oftunneling barriers. These are presented in detail below when we describethe following specifics: (1) controlled formations of quantum wellsthrough material selections and interface engineering of dielectriclayers; (2) formation of an electron energy filtering structure using avertical electrode configuration and semiconductor or metalnanoparticles; (3) formation of an electron energy filtering structureusing nanopillars; and (4) design and fabrication of “two-terminal”device configurations (having source and drain, but without the gate)and “three-terminal” device configurations (transistors).

Quantum wells are created by manipulating the energy band bending of thematerials involved. This requires an appropriate selection of materialsand their proper geometrical arrangement, as well as engineering theinterfaces between the material layers. The present invention satisfiesthe following goals: (1) obtain the capability of creating andeliminating the electron energy filtering structure at our disposal; (2)elucidate key parameters that control the degree of energy filtering;and (3) fabricate the optimum energy filtering structure and obtaineffective temperature lowering by a factor of 6.5 or higher.

The suppressed FD smearing in FIGS. 2-4 and 13 was observed for amaterial system made of Cr, Cr₂O₃, and SiO₂. By using proper materialsystems and structures, the energy filtering effect and suppression ofFD smearing can be further enhanced. The formation of quantum wellenergy states and the filtering effect depend on four parameters: theenergy barrier (E_(b)), the degree of band bending (E_(bend)), and thethicknesses of tunneling barrier 1 (d₁) and tunneling barrier 2 (d₂)shown in FIG. 14. Here, the key requirement for the energy filtering isthat the band bending E_(bend) needs to be larger than the energybarrier E_(b). Otherwise, the discrete energy levels formed in thequantum well would be located higher than the Fermi level of the sourceelectrode E_(F); for the energy filtering, the discrete energy levelformed in the quantum well needs to be located close to the Fermi levelof the electrode. Using this energy landscape and also assisted bytunneling transmission coefficient calculations, various materials andstructures can be evaluated and the optimal system that produces themaximum suppression of FD or the lowest effective electron temperaturecan be identified.

Some examples of selecting optimal systems are given here. The Tablebelow shows several material systems that were selected based on thesize of energy barrier E_(b) (the energy barrier between the sourcemetal and the barrier 1 in FIG. 14), which ranges from 1.6-2.5 eV forAl/Al₂O₃ to 0.02 eV for Pb/Cr₂O₃.

Material System (Source/Barrier 1) E_(b) (eV) Al/Al₂O₃ 1.6-2.5 Pb/Cr₂O₃0.02 Cr/Cr₂O₃ 0.06 Ti/TiO_(x) 0.285The role of energy barrier E_(b) on the formation of energy filteringstructure as schematically displayed in FIGS. 15A-15B will be described.For example, if Al/Al₂O₃ system is used (its barrier height is 1.6-2.5eV, at least a factor of 10 higher than that for Cr/Cr₂O₃ system), noenergy filtering is expected to occur unless the band bending isappreciably large (>1.6-2.5 eV); if the energy levels formed in thequantum well, they would be located far above the electrode Fermi level,FIG. 15A. The energy filtering can, however, be obtained for this systemby creating a band bending E_(bend) higher than the energy barrier E_(b)using various methods described in following sections. The Al/Al₂O₃system can be compared with the Cr/Cr₂O₃ system, for which the energybarrier E_(b) is appreciably lower, ˜0.1 eV; upon a small band bending,a discrete state which is close to the electrode Fermi level is formedin the quantum well, FIG. 15B. So, by using appropriate materialssystems and appropriate band bendings, the energy filter can be turnedon or off. This energy filtering can be assessed through the I-Vmeasurement. If the energy filter is on, a room-temperature I-Vmeasurement will produce abrupt current jumps, FIG. 15B (bottom). If theenergy filter is off, the room-temperature I-V would not produce anyabrupt current jumps due to the usual FD thermal smearing, FIG. 15A(bottom).

Another critical factor for the formation of a quantum well is thedegree of band bending E_(bend) in FIG. 14. The band bending will dependon the following factors: (1) the work functions of the materials used(electrode, tunneling barrier 1, tunneling barrier 2, and semiconductoror metal nanoparticle); and (2) the interface dipoles and/or interfacecharges created at the interfaces of the films. The former can bedetermined by the material selection, and the latter can be controlledby introducing dipolar molecules at the interface and/or treating thesurfaces with UV/Ozone or plasma. The interface dipoles and/or interfacecharges can also be formed spontaneously at the interface of thetunneling barrier 1 and tunneling barrier 2 by properly selecting thetwo barrier materials. Manipulating the interface dipoles and/orinterface charges and associated band bending is described below.

To form a quantum well, the conduction band of the barrier 1 needs to bebent downward (FIG. 14). As the first approach, this band bending iscontrolled by forming dipolar SAMs on the surface of barrier 1 (theinterface between the barrier 1 and barrier 2). It is well appreciatedthat the modification of surfaces or interfaces by molecules or atomscan dramatically change the electronic properties of materials [61-67].For example, it has been demonstrated experimentally and theoreticallythat the adsorption of atoms on the surface can change the work functionof metals as much as >2 eV [68, 69]. The change of work function bymonolayer or submonolayer coverage of dipolar SAMs can also be verysubstantial, more than 0.5 eV [61, 62, 65, 66, 70]. With these bandbendings, along with a proper selection of the material system (whichdetermines the energy barrier E_(b)), a quantum well and a discreteenergy state can be made to form near the electrode Fermi level E_(F),FIG. 15B.

FIG. 16 shows a schematic of controlling the band bending of barrier 1using SAMs of different polarities. Depending on the direction of thedipole moment of the SAMs and/or the polarity of the interface charges,the band bending of the tunneling barrier 1 can occur either downward orupward direction, FIGS. 16b .1 and 16 b.2, respectively. Upon placingtunneling barrier 2 (e.g., SiO₂) on the SAMs, the former can lead to acreation of a quantum well and a discrete energy level (FIG. 16c .1),whereas the latter will not produce a quantum well (FIG. 16c .2).Through this manipulation of interface dipoles and/or interface charges,the energy filter can be turned on and off as desired. This not onlyelucidates the detailed mechanism of the observed suppression ofFermi-Dirac smearing and effective temperature lowering, but also leadsto the capability of controlling the energy filtering with greatprecision. A broad spectrum of interface dipoles and/or interfacecharges can be obtained by using various molecules that have differenthead groups, chain lengths, and anchor groups [62, 65, 66]. Formation ofinterface dipoles and/or interface charges will be characterized usingKelvin probe force microscopy (KPFM) and/or X-ray photoelectronspectroscopy (XPS) [71-73].

The other techniques to create and control the interface dipoles and/orinterface charges are UV/Ozone or plasma treatment of the surfaces[74-76]. The interface dipoles and/or interface charges created canchange the work function as high as 2 eV [74, 77]. These techniques,possibly in conjunction with the SAMs formation, can be used to controlthe band bending, and therefore to create the energy filtering structureof this invention.

To create downward band bending and to create the energy filteringstructure of this invention, FIG. 15B, we can also utilize thespontaneous interface dipole formation that occurs for many materialsystems of barrier 1 and barrier 2. For example, Cr₂O₃ and SiO₂ can beused for barrier 1 and barrier 2 materials in FIG. 15B, respectively,for which the spontaneous formation of interface dipoles at theinterface of Cr₂O₃ and SiO₂ layers produces a desired dipole direction(positive pole in barrier 1 side and negative pole in barrier 2 side)and therefore the desired downward band bending.

Controlling the electron energy filtering for cold electron transport asdescribed above can be incorporated into many different configurations.Two cases are described below as examples. The first approach is tobuild energy filtering electronic devices that use a vertical electrodeconfiguration and semiconductor or metal nanoparticles. The secondapproach employs a nanopillar configuration in which all the electrodes,tunneling barriers, and energy filtering structure reside in a singlenanopillar. The following sections describe these two approaches.

A schematic of the first approach is shown in FIGS. 17A-17C with amagnified view of the region where the energy-filtered tunneling willtake place. By closely looking at the electron tunneling path (indicatedby an arrow) from the source electrode to the QD (semiconductornanoparticle), it is important to note that electrons go through twotunneling barriers, barrier 1 and barrier 2. The barrier 1 is a nativeoxide that naturally forms on the surface of metal electrode. Utilizingnative oxides of metals for the barrier 1 is beneficial since qualityfilms with consistent thickness can be obtained. Many metals form nativeoxides. The candidate electrode metals that we can use include Cr, Al,Ti, Ta, and Mo. For the tunneling barrier 2, a dielectric material whoseconduction band edge lies much above the conduction band edge of thebarrier 1 is used. This is to ensure that a quantum well is formed whenthe downward band bending of barrier 1 takes place. Candidate materialsfor barrier 2 include SiO₂ and Si₃N₄. The barrier 2 is deposited on thesurface of barrier 1 using deposition techniques such as sputtering,plasma-enhanced chemical vapor deposition (PECVD), and atomic-layerdeposition (ALD). Prior to deposition of barrier 2, the surface ofbarrier 1 may be treated with SAMs or plasma to form interface dipolesand to produce an appropriate band bending of the barrier 1 as describedin the previous section. Alternatively, the spontaneous interface dipoleformation at the interface of barrier 1 and barrier 2 can be used tocreate the appropriate band bending and to create the energy filteringstructure as described above.

In the second approach, a nanopillar configuration is used to create theelectron energy filtering structure and to fabricate energy-filteredcold electron devices. In the nanopillar configuration, all the devicecomponents (electrodes, tunneling barriers, quantum dot/semiconductornanocrystal) reside in a single nanopillar. FIG. 18 shows a nanopillarconfiguration that is composed of source (Cr), a first tunneling barrier(Cr₂O₃), a second tunneling barrier (SiO₂), Si island, an additionalsecond tunneling barrier (SiO₂), an additional first tunneling barrier(Cr₂O₃), and drain (Cr). The nanopillar contains two tunneling barriersbetween the source and the Si island; Cr₂O₃ for the first tunnelingbarrier and SiO₂ for the second tunneling barrier. As previouslydescribed, the band bending in the Cr₂O₃ (the first tunneling barrier)conduction band leads to a formation of a quantum well and a discretestate in the quantum well, creating the energy filtering structure.Other material combinations can also be used to construct the energyfiltering structure in a nanopillar.

The merit of using nanopillar structure is that accurate dimensionalcontrol is possible such as the thickness of the tunneling barriers anddistances between the components in a stack of electrode/tunnelingbarriers/quantum dot/tunneling barriers/electrode. Furthermore,arranging the device components within a nanopillar and theirdimensional control in the nanopillar can be very versatile; forexample, different series of device components can be put in nanopillarsin relatively simple procedure. These merits come from the fact thatnanopillars are fabricated from a stack of films, for which thethickness can be accurately controlled with sub-nanometer scaleprecision.

Nanopillar structures can be fabricated as follows. A stack of materiallayers are made by deposition or oxidation/nitridation, and then ananoparticle is placed on top of the film stack as shown in FIG. 19A.Each tunneling barrier layer in the schematic may comprise of multiplebarriers (e.g., a first tunneling barrier and a second tunnelingbarrier) and also interface dipole SAMs between them. Using thenanoparticle as an etching hard mask, the film stack is verticallyetched by reactive ion etching (RIE), producing a nanopillar as shown inFIG. 19B. The nanoparticle on top of the nanopillar is selectivelyremoved using chemical etching, producing the final nanopillar structurethat contains all the device components (electrodes, tunneling barriers,etc) as shown in FIG. 19C. FIG. 19D is an SEM image of a nanopillar thatwas fabricated with procedure in FIGS. 19A-19C. This nanopillar wascomposed of Cr source, Cr₂O₃ tunneling barrier, Cr island, Cr₂O₃tunneling barrier, and Cr drain. The individual Cr₂O₃ barriers could notbe resolved with SEM.

The thicknesses of the device components in a nanopillar (e.g.,tunneling barrier thickness) can be accurately controlled since they aredetermined by the layer thicknesses formed in the first step in FIG.19A; the layer thickness can be controlled with sub-nanometer scaleprecision using techniques such as ALD and PECVD. By choosing thematerials deposited and by accurately controlling their thicknesses inthe first step (FIG. 19A), a variety of nanopillars can be fabricated.

The electron tunneling characteristics are assessed by I-V and dI/dV(lock-in) measurements at varying temperatures. Electrical contacts tothe nanopillar are made using usual CMOS fabrication procedure, whichinclude deposition of passivation material (e.g., SOG: spin-on-glass),photolithography, RIE, and metal deposition. FIGS. 20A-20D show theprocess flow to make electrical contacts to the nanopillar. FIG. 20Ashows deposition of passivation material (e.g., SOG: spin-on-glass).FIG. 20B shows RIE etching to expose the top portion of the nanopillar.FIG. 20C shows formation of a drain pad which makes an electricalcontact with the nanopillar. The drain pad is formed usingphotolithography, metal deposition, and lift-off. FIG. 20D showsformation of vias and metal interconnects. This is made by deposition ofanother layer of passivation material (e.g., SOG: spin-on-glass), makingvias with photolithography and RIE etching, filling the vias with metaldeposition, and formation of bond pads using photolithography, metaldeposition and lift-off.

The capability of effectively suppressing the Fermi-Dirac thermalsmearing and accompanying effective temperature lowering can be utilizedto obtain electronic devices that can operate with extremely-low powerconsumption. Thermodynamics (FD distribution) imposes a low bound ontransistors' subthreshold swing (SS), the measure of how abruptly atransistor can be turned off below the threshold voltage V_(th). With alow subthreshold swing (for which transistors can be turned offabruptly), the supply voltage V_(DD) can be reduced and hence the powerconsumption (proportional to the square of V_(DD)) while maintaining alow OFF-state current. For current transistor architecture, however, thethermodynamics sets the lowest possible subthreshold swing to 60mV/decade at room temperature [7, 78, 79], and V_(DD) cannot be reducedmuch smaller than one volt without having a significant OFF-statecurrent. This imposes an intrinsic limit on reduction of powerconsumption during transistor operation. Thermodynamics tells that thesubthreshold swing SS is proportional to the temperature T, SS=ln10·(kT/e). The ability of this invention to obtain low effectiveelectron temperature through electron energy filtering can produce a lowSS since it is proportional to the electron temperature. The low SSallows a use of smaller supply voltage V_(DD), allowing device operationwith extremely-low power consumption. As previously described, theeffective electron temperature is 45 K when the reservoir temperature isroom temperature (295K), making SS as small as 10 mV/decade at roomtemperature. With this SS, power consumption can be reduced by a factorof 100 compared to that for current state-of-the-art CMOS transistors.

The previous sections described electron energy filtering and associatedeffective electron temperature lowering in two-terminal configuration,i.e., without the gate. Here, fabrication procedures to add gateelectrodes to make three-terminal devices, i.e., the transistors, aredescribed. Two different transistor configurations are described: (1)transistors employing vertical electrode configuration and semiconductornanoparticles; and (2) transistors using nanopillar configuration. Wename these transistors “energy-filtered cold electron transistors”.

Energy-filtered cold electron transistors are fabricated by adding gateelectrodes to the two-terminal device structure previously discussed.FIG. 21 displays a schematic of the transistor structure, in which agate electrode encompasses the periphery of the source/insulatinglayer/drain stack. This gate addition will be made throughphotolithography and gate metal deposition before forming the vias andbond pads. The use of photolithography along with other CMOS-compatibleprocess steps allows production of individually addressable gates andlarge-scale parallel fabrication of the energy-filtered cold electrontransistors.

It is important to check if the gate design in FIG. 21 gives the desiredgating power (allowing responsive gate modulation of the I-Vcharacteristics) and also whether the gate structure can be reliably andreproducibly fabricated with a small device-to-device variation. Theprevious work on fabricating single-electron transistors (SETs) supportsthat this is the case [26]. For this SET fabrication, essentially thesame configuration as in FIG. 21 was used, except that metalnanoparticles (˜10 nm Au nanoparticles) were used instead ofsemiconductor nanoparticles. FIG. 22A shows the modulation of thecurrent as to a function of gate voltage. A clear Coulomb oscillation(periodic change of the current as a function of gate voltage) can beseen, which demonstrates that the gate design in FIG. 21 can deliver thedesired gating power. The device-to-device variation was also checked bymeasuring the Coulomb interval ΔV_(G) (peak-to-peak distance in theCoulomb oscillation; indicated by the arrow in FIG. 22A) for tendifferent SETs fabricated in a single batch. FIG. 22B displays ΔV_(G)from these SETs and shows that the device-to-device variation is lessthan 10%. These demonstrate that our gate structure in FIG. 21 can bereliably fabricated with CMOS-compatible processes and materials andproduce a responsive gating power.

One of the performance goals of the energy-filtered cold electrontransistor is to obtain subthreshold swing (SS) of 10 mV/decade or lessat room temperature. The subthreshold swing is the measure of “gatevoltage” change required to reduce the source-drain current by a factorof 10. Although a gate electrode is needed to measure the subthresholdswing of a transistor, I-V measurements for a two-terminal device (withno gate electrode) can also give clear information whether a targetedsubthreshold swing is achievable or not when a gate is added. Forexample, if the source-drain current of a device can be turned down by afactor of 10 with a source-drain voltage change of 10 mV, a subthresholdswing of 10 mV/decade can be obtained as long as the gate coupling tothe semiconductor nanoparticle is sufficiently high. We obtained thiscapability as described below.

An energy-filtered cold electron device with the two-terminalconfiguration as in FIG. 17 was fabricated using Cr₂O₃ and SiO₂ as thetunneling barrier 1 and tunneling barrier 2, respectively. A CdSe QDwith a diameter of ˜6 nm was used as the semiconductor nanocrystal. FIG.23A shows its I-V characteristics measured at room temperature. A verysteep increase of electrical current (see the red dotted square) can beseen which corresponds to the alignment of the QW energy level ε_(W)with the conduction band edge of the CdSe QD (1st energy state of the QDin the conduction band). FIG. 23B is a zoomed-in view of the steepcurrent change in log scale and demonstrates that the slope is ˜10mV/decade. This data demonstrates that if a gate with a sufficientcapacitive coupling with the QD is added to produce a transistor, FIG.21, a subthreshold swing of 10 mV/decade can be obtained at roomtemperature. With further optimization of the electron energy filtering,effective electron temperatures can be further reduced below 45 K atroom temperature and a subthreshold swing of less than 10 mV/decade canbe realized at room temperature.

This section describes fabricating energy-filtered nanopillar coldelectron transistors by inserting the gates into the two-terminalnanopillar devices shown in FIG. 20D. FIGS. 24A-24B show schematics of acompleted energy-filtered cold electron nanopillar transistor with agate electrode incorporated. In this configuration, the gate electrodesurrounds the semiconductor island of the nanopillar, controlling itselectrostatic potential. The procedure to achieve this configuration isschematically displayed in the cross-sectional view around thenanopillar in FIGS. 25A-25J. After nanopillar formation on the sourcepad, a conformal film of an insulating material (gate dielectric; e.g.,SiO₂) is deposited using PECVD or ALD in FIG. 25A. The conformaldeposition ensures that the same thickness of the insulating material isdeposited on the side of nanopillar as on other planar surfaces. Themetal for gate electrode (e.g., Cr, Al, and Ti) is deposited (e.g.,using sputtering) onto the wafer, producing a semi-conformal film on topof the gate dielectric film in FIG. 25B. If necessary, the wafer may beconstantly tilted and rotated during the sputter deposition, making themetal film more conformal. A passivation material is deposited, thickenough to cover all the nanopillars (the surface is planarized), in FIG.25C. A planarized surface can be obtained either through spin-coating ofspin-on glass (SOG) or using chemical-mechanical polishing (CMP). Thepassivation material is vertically etched using RIE until the gate metalfilm (in red) surrounding the drain portion of the nanopillar is wellexposed in FIG. 25D. The exposed gate metal film is then selectivelyremoved by wet chemical etching, exposing gate dielectric layersurrounding the drain portion of nanopillar in FIG. 25E. The exposedgate dielectric layer is subsequently removed by wet chemical etching,exposing the drain portion of the nanopillar in FIG. 25F. At this point,the gate metal (the red film) covers all the substrate surfaces. Thegate metal is patterned to produce the gate structure in FIGS. 24A-24B.This is done using photolithography and RIE in FIGS. 25G-25H. With theprocedure in FIG. 20C, the drain pad is fabricated in FIG. 251. Thewafer is then passivated in FIG. 25J, which is followed by theconstruction of interconnection lines, producing the finalenergy-filtered cold electron nanopillar transistor structure in FIGS.24A-24B.

Energy-filtered cold electron nanopillar transistors that areindividually addressable can be fabricated on a large scale. Oneessential requirement to achieve this is the capability of placingsingle nanoparticles (used for etching hard mask) on exact targetlocations on the substrate, FIG. 19A. This is achieved using atechnique, named single-particle placement (SPP), in which singlenanoparticles are electrostatically guided and placed on the targetlocations with nanoscale precision [60]. An SEM image in FIG. 26A showsthe capability of the SPP; exactly one nanoparticle is placed on thecenter of each circular guiding pattern. The SPP can be utilized toprecisely place single nanoparticles on exact target locations in asingle batch process on an entire wafer, FIG. 26B, from whichindividually addressable nanopillar tunnel transistors can be created inparallel over an entire wafer, FIG. 26C.

The methods described above for the fabrication of the structures inFIG. 17 and FIG. 21 will now be briefly summarized. The device unitswere fabricated on Si wafers using CMOS-compatible processes andmaterials. The fabrication was carried out in the class 1000 cleanroom.Starting with a four inch silicon wafer, silicon oxide of ˜1.5 μm wasthermally grown for electrical isolation of the devices. Over theisolation oxide layer, bottom electrodes (Cr) were made usingphotolithography (Negative photoresist NR9-1000PY; Futurrex), depositionof ˜200 nm thick Cr and lift-off. The insulating layers (SiO₂ or Al₂O₃)were deposited using plasma-enhanced chemical vapor deposition (PECVD)or atomic-layer deposition (ALD). The thicknesses of the insulatinglayers were 4.5 nm-10 nm, with the thinner layer for smallernanoparticles (˜5.5 nm CdSe) and the thicker layer for largernanoparticles (˜10 nm Au). The top electrodes (Cr) were put on theinsulating layer using the second photolithography step (Negativephotoresist NR9-1000PY; Futurrex), ˜200 nm thick Cr metal deposition andlift-off. The top electrodes were positioned on top of the bottomelectrodes using the alignment marks in the photomasks. Using the topelectrodes as the hard mask, the insulating layer was then verticallyetched away by reactive ion etching (RIE) with CF₄ chemistry. The RIEplasma etch created top electrode/insulating layer/bottom electrodestacks that were vertically aligned. Then, CdSe quantum dots or the Aunanoparticles were attached on the exposed sidewall of the insulatinglayer in the top electrode/insulating layer/bottom electrode stack.After the nanoparticle attachment the device units were passivated with˜300 nm thick sputtered silicon oxide, followed by the final passivationwith ˜700 nm thick e-beam evaporated silicon oxide. For single-electrontransistor fabrications, the gate electrodes were inserted before thefinal passivation step. The gate patterns were defined using anadditional photolithography step (Negative photoresist NR9-1000PY;Futurrex), followed by ˜350 nm thick Cr deposition and lift-off. To formthe metal contact to bottom electrodes, top electrodes and gateelectrodes, the Via-holes were created by the RIE etching of thepassivation silicon oxide. Finally the bond pads were defined usingphotolithography, followed by evaporation of ˜100 nm Cr and ˜250 nm Au,and lift-off.

Procedure to attach semiconductor or metal nanoparticles onto theexposed sidewall of the insulating layer is described here. Thesubstrate was functionalized with self-assembled monolayers (SAMs) of3-aminopropyltriethoxysilane (APTES: (C₂H₅O)₃—Si—(CH₂)₃—NH₂). The APTES(99%) was purchased from Sigma-Aldrich and used without furtherpurification. The SAMs of APTES were formed by immersing the substratein 1 mM APTES solution in ethanol for 30 minutes at room temperature.The substrate was then rinsed with pure ethanol, followed by drying withnitrogen. The ˜7 nm and ˜5.5 nm CdSe nanoparticles in toluene werepurchased from NN Labs. The ˜10 nm Au nanoparticle colloid was purchasedfrom Ted Pella. The APTES functionalized substrates were immersed in theCdSe or Au nanoparticle colloids at room temperature for 8-24 hours.CdSe or Au nanoparticles were attached on the exposed sidewall of theinsulating layer as well as other exposed surfaces. Only thenanoparticles that were attached on the exposed sidewall and were in theright tunneling range from both electrodes contributed to the electricalsignal. After attachment of CdSe or Au nanoparticles, the wafers wereexposed to UV ozone (PSD-UVT, NovaScan) for 30 minutes at roomtemperature. After the UV ozone treatment, the wafers were immediatelytransported into the vacuum chamber for silicon oxide passivation.

Here we describe key elements that can lower electron temperature evenfurther and make the energy-filtered cold electron transport morepowerful. In principle, if there is no nearby energy state in the QW towhich the electron can be thermally excited, the tunneling of anelectron from the source electrode to the QW state leaves the electronat zero temperature [8, 9]. Furthermore, if the electron does not gainenergy during the subsequent tunneling event to the QD, the electrontemperature would remain effectively at zero Kelvin. If these twoconditions were fulfilled, electron transport at extremely-low electrontemperatures can be obtained. The first condition can be satisfiedrelatively easily since the energy level separation in the QW can bemade much larger than the room temperature thermal energy [16, 23]; witha thin (<2 nm) layer thickness of the barrier 1 in FIG. 14, the energylevel separation of the QW becomes much larger (>a few hundred meV) thanthe room temperature thermal energy (˜25 meV). The second condition,i.e., blocking energy-gaining pathways, can be fulfilled by controllingthe factors that affect the phonon absorption. For example, the phononabsorption can be minimized by lowering the effective Debye cutofffrequency. This can be achieved by proper selection of materials for QD,dielectric, passivation layers, etc. and proper design of devicedimensions (e.g., QD size) and geometric configurations.

Out of many breakthroughs of this invention described in the previoussections, two of them are specifically noted below as they haveimmediate relevance to practical applications.

First, our invention allows energy filtering and effective cooling ofelectrons “without any external cooling”, i.e., the energy filtering canbe carried out “at room temperature”. Furthermore, the temperaturelowering can be as much as 250 degrees (295K−45K=250K) even the systemis operated at room temperature. This unique capability of thisinvention may be compared with previous works by others in which theelectron temperature is effectively lowered only when the entire systemis cooled to cryogenic temperatures, typically less than 1 Kelvin[8-15]. This requirement of external cooling using cryogens (liquid Heor liquid N₂) or cryogenic cooling systems severely limits practicalapplications.

Second, our invention allows a large-scale parallel fabrication ofenergy-filtered cold electron devices using CMOS-compatible processesand materials. All the energy-filtered cold electron device structurespreviously described (FIGS. 1C, 17, 18, 19, 20, 21, 24, 25, and 26) canbe fabricated using CMOS-compatible processes and materials. Thisimportant advantage of present invention may be compared with previousworks by others [8-15] in which materials and processes used are notCMOS-compatible and a large-scale fabrication is difficult to achieve.

The present invention provides a transformative technology thateffectively suppresses the Fermi-Dirac distribution of electrons, inwhich electron energies are filtered and very low electron temperatures(<45 K) are obtained without any physical cooling. With this effectivetemperature lowering, many novel electronic, optoelectronic, andspintronic devices that can currently function only at cryogenictemperatures will be able to operate at room temperature without anyexternal cooling. Furthermore, the low electron temperature candramatically enhance the performance of many electronic, optoelectronic,and spintronic devices at room temperature. One important example amongmany potential military, commercial, and space applications is toutilize the electron energy filtering and effective temperature loweringto fabricate transistors that can operate with extremely-low powerconsumption (green transistors), cutting the energy consumption by afactor of >100. This means that electronic equipment can function withonly 1% of power resources or the battery weight of an instrument andcan be reduced by a factor of >100, without sacrificing the performance.This capability would generate numerous military applications, examplesinclude: unmanned aerial vehicles (UAVs), remote communication devices,remote sensing devices, missiles, submarines, aircrafts, and electronicdevices that marines carry in their missions. Impact to commercialdevice applications is also expected to be immense; for example, cellphones and laptops that can operate for a month without recharging canbe realized.

Various new transistor architectures using the room-temperature energyfilter of the present invention will now be described.

One of the key elements of the invention is to create a quantum welladjacent to an electrode. The discrete energy level in the quantum wellcreated serves as the energy filter. In the exemplary structure composedof Cr/Cr₂O₃/SiO₂, the quantum well is formed through band bending of theCr₂O₃ conduction band. Direct evidence of quantum well formation isprovided by directly measuring the amount of band bending of thechromium oxide layer which resides between the Cr electrode and SiO₂layer. This is done by fabricating a metal-insulator-semiconductor (MIS)structure in which the insulator is composed of Cr₂O₃/SiO₂ layers andcarrying out C-V (capacitance-voltage) measurements of the fabricatedMIS units. The C-V measurement of the MIS structure is awell-established technique that can directly measure the energy bandbending of the insulating layer [81-84]. The amount of band bending ofthe Cr₂O₃ layer was obtained from the flat band voltage shift (ΔV_(FB))in the C-V plot for MIS units having varying Cr₂O₃ thicknesses. For ˜2nm Cr₂O₃ (the thickness of native chromium oxide used in the CdSe QDdevices and SETs), the ΔV_(FB) is measured to be −1.1±0.1 V, meaningthat the depth of the Cr₂O₃ quantum well of the devices is 1.1±0.1 eV.The detail of the experimental measurements is described below.

FIG. 27 shows a schematic of the MIS structure for a direct measurementof the energy band bending of the Cr₂O₃ layer in accordance with oneembodiment of the present invention. The materials used for the MIS areas follows. For the semiconductor, a p-type Si substrate (sheetresistance: 1-25 Ω·cm) was used. On top of the Si substrate, 5 nm SiO₂layer was sputter-deposited with a slow deposition rate of 0.17 nm perminute (AJA Orion UHV System). On top of the SiO₂ layer, a Cr₂O₃ layerwas sputter-deposited in-situ with a deposition rate of 0.25 nm perminute (AJA Orion UHV System). Here the thickness of the Cr₂O₃ layer wasvaried with 3 different conditions: 0 nm (no Cr₂O₃ layer), 2 nm and 5nm. Then, a Cr metal electrode was deposited using the photolithographyand lift-off.

The C-V measurements were carried out with an AC modulation frequency of1 MHz. FIG. 28A shows the measured C-V characteristics for the MIS unitshaving Cr₂O₃ layer thicknesses d_(Cr2O3)=0 nm (blue), 2 nm (red) and 5nm (green) (each C-V line is a measurement from a different MIS unit).The C-V data shows that the flat band voltage V_(FB) is shifting in thedirection of increasing negative voltages with increasing Cr₂O₃ layerthicknesses d_(Cr2O3). The flat band voltage V_(FB) is defined as thevoltage V_(G) at which the C/Co is 0.8 (the dashed line). ΔV_(FB) (inred in FIG. 28A) is the flat band voltage shift for d_(Cr2O3)=2 nm,i.e., ΔV_(FB)=V_(FB) (d_(Cr2O3)=2 nm)−V_(FB) (d_(Cr2O3)=0 nm). C/Co isnormalized capacitance, where Co is the total capacitance of theCr₂O₃/SiO₂ layers (1/Co=1/C_(Cr2O3)+1/C_(SiO2)). The flat band voltagesV_(FB) with varying Cr₂O₃ thicknesses d_(Cr2O3) are summarized in FIG.28B. The V_(FB)'s are from the C-V measurements in FIG. 28A. A linearrelationship is found with R² value of 0.98. This linear relationship isin good agreement with the known relationship between the flat bandvoltage shift and the insulating layer thickness [81-84];ΔV _(FB)(d _(Cr2O3))=−Q _(i) /C _(Cr2O3)=−(Q _(i)/ε_(Cr2O3))×d_(Cr2O3)  (42)Q_(i) is the effective interface charge density at the Cr₂O₃/SiO₂interface, C_(Cr2O3) is the capacitance per unit area of the C_(Cr2O3)layer, and ε_(Cr2O3) is the permittivity of Cr₂O₃.

From the C-V measurements in FIGS. 28A-28B, the following is noted.First, the negative shift of V_(FB) with increasing Cr₂O₃ thicknessesshows that the energy band bending of the Cr₂O₃ layer occurs in thedirection to form a quantum well, i.e., the Cr₂O₃ energy band goes downas it approaches the Cr₂O₃/SiO₂ interface. Second, the magnitude of theflat band voltage shift ΔV_(FB) for 2 nm Cr₂O₃ is about 1 volt orlarger, FIG. 28A. More quantitatively, ΔV_(FB) is −1.1±0.1 V from thelinear regression in FIG. 28B:

$\begin{matrix}\begin{matrix}{{\Delta\; V_{FB}} = {\left( {d_{{cr}\; 2O\; 3} = {2\mspace{14mu}{nm}}} \right) = {{V_{FB}\left( {d_{{cr}\; 2O\; 3} = {2\mspace{14mu}{nm}}} \right)} -}}} \\{V_{FB}\left( {d_{{cr}\; 2\; O\; 3} = {0\mspace{14mu}{nm}}} \right)} \\{= {{0.5327 \times 2} = {- {{1.0624\lbrack V\rbrack}.}}}}\end{matrix} & (43)\end{matrix}$From the above, the depth of the quantum well formed in 2 nm Cr₂O₃ layeris 1.1±0.1 [eV].

The linear relationship in FIG. 28B and its excellent agreement with theequation (42) prove that for the Cr/Cr₂O₃/SiO₂ system shown here as anexample, the interface charges at the Cr₂O₃/SiO₂ interface areresponsible for the quantum well formation, and eventually for theenergy filtering. The interface charges are spontaneously formed duringthe fabrication process and the amount of the interface charges createddepends on the process condition, for example, the process parameters(pressure, RF power, gas flow rate, etc.) for the SiO₂ deposition. Thismeans that by engineering the process parameters the amount of interfacecharges can be controlled, which in turn control the amount of the bandbending, the depth of quantum well, and the positions of the quantumwell energy levels, eventually determining the characteristics (e.g.,the effective electron temperature) of the energy filtering.

In summary, the energy band bending of the Cr₂O₃ layer has been directlymeasured by fabricating MIS units having varying Cr₂O₃ thicknesses andcarrying out C-V measurements of the MIS units. The negative values ofthe flat band voltage shift ΔV_(FB) show that the band banding of theCr₂O₃ layer occurs in the direction to form a quantum well. The depth ofthe quantum well for the 2 nm Cr₂O₃ layer is measured to be 1.1±0.1[eV].

Another important element that enables the room-temperature energyfiltering of the present invention is the large separation betweenquantum levels in the QW energy filter. For energy filtering through aquantum state to work at room temperature, the level spacing betweenadjacent quantum levels in the energy filter must be appreciably largerthan room-temperature thermal energy, ˜25 meV. The narrow quantumconfinement in the QW layer is able to produce large energy levelseparations because a QW can reliably be made very thin, a fewnanometers. For the chromium oxide QW of the present invention, itsthickness (˜2 nm) along with its QW depth (˜1 eV) produces energy levelspacing larger than 250 meV. This level separation is more than tentimes larger than room-temperature thermal energy, makingroom-temperature energy filtering possible.

An added practical benefit to the QW energy filter of the presentinvention is its facile formation. For the chromium oxide QW used, theoxide is spontaneously formed on the chromium electrode surface, arelatively simple and controllable procedure. In addition, the materialsused in the QW energy filter formation (e.g., Cr, Cr₂O₃ and SiO₂) arecompatible with mainstream CMOS materials and processes. This CMOScompatibility is an important attribute that is essential for a broadrange of practical device applications.

A variety of new transistor architectures can be created using theroom-temperature energy filter of the present invention. The energyfilter is positioned adjacent to an electrode and filters out thermallyexcited energetic electrons in the electrode as they are transported tothe central island and eventually to the other electrode. A gateadjacent to the central island controls the electrostatic potential ofthe central island and thereby controls electron transport. Theroom-temperature energy filter of the present invention can be used tocreate a variety of new transistor structures since the energy filterscan be implemented into many different configurations. Two examples havebeen described in the previous sections, one using vertically stackedsource/insulating layer/drain configuration with the central islandattached on the sidewall of the insulating layer, the other using thenanopillar structure. Another example is described here that uses aplanar configuration in which source, energy filter, a central island,and drain are positioned in a planner configuration.

FIG. 29 shows a schematic (not to scale) of an energy-filtered coldelectron transistor in a planer configuration that utilizesroom-temperature energy filter in accordance with the present invention.The room-temperature energy filter is positioned between an electrodeand the central island. The room-temperature energy filter is formed ina configuration made of a sequential arrangement of an electrode, firsttunneling barrier, second tunneling barrier, and a central island. Thequantum well is formed in the first tunneling barrier using energy bandbending and a discrete level of the quantum well serves as the energyfilter. The gate electrode located on top of the central island controlsthe electrostatic potential of the central island and controls theelectron transport from one electrode to the other.

More specifically, the energy-filtered cold electron transistor includesa central island, a second tunneling barrier, an additional secondtunneling barrier, a first tunneling barrier, an additional firsttunneling barrier, a first electrode, a second electrode, a gatedielectric and a gate electrode. The central island is disposed on anisolation layer and has at least a first wall and a second wall. Thecentral island can be a bulk semiconductor material, a semiconductornanoparticle, a metal nanoparticle, an organic material, an inorganicmaterial, a magnetic material, or a superconducting material. The secondtunneling barrier is disposed on the first wall of the central island.The additional second tunneling barrier is disposed on the second wallof the central island. The first tunneling barrier is disposed on thesecond tunneling barrier and a first portion of the isolation layer. Theadditional first tunneling barrier is disposed on the additional secondtunneling barrier and a second portion of the isolation layer. The firstelectrode is disposed on the first tunneling barrier above the firstportion of the isolation layer and adjacent to the first tunnelingbarrier disposed on the second tunneling barrier. The second electrodeis disposed on the additional first tunneling barrier above the secondportion of the isolation layer and adjacent to the additional firsttunneling barrier disposed on the additional second tunneling barrier.The gate dielectric is disposed above a portion of the first electrode,the first tunneling barrier, the second tunneling barrier, the centralisland, the additional second tunneling barrier, the additional firsttunneling barrier and a portion of the second electrode. Alternatively,the gate dielectric is disposed only above the central island. The gateelectrode is disposed on the gate dielectric.

An energy-filtered cold electron transistor, comprising a firstelectrode, a second electrode, a gate electrode and an electron energyfilter (quantum well) disposed between the first electrode and thesecond electrode, operates by filtering out any thermally excitedelectrons using the electron energy filter by a discrete state of thequantum well at room temperature, transporting only energy-filtered coldelectrons between the first and second electrodes, and controlling thetransport of the energy-filtered cold electrons using the gateelectrode. The energy-filtered cold electrons are produced with aneffective electron temperature of 45 K or below at room temperatureusing the electron energy filter without any external cooling. Theenergy-filtered cold electron transistor produces extremely steepcurrent turn-on and turn-off capability, wherein the energy-filteredcold electrons with an effective electron temperature of 45 K or belowproduce a subthreshold swing of less than or equal to 10 mV/decade atroom temperature. The energy-filtered cold electron transistor can havea supply voltage of less than or equal to 0.1 V.

The electron energy filter is formed from a sequential arrangement ofthe first electrode, a first tunneling barrier and a second tunnelingbarrier. The quantum well is formed in the first tunneling barrier and adiscrete quantum state or multiple number of discrete quantum states areformed in the quantum well. A depth of the quantum well is controlled byenergy band bending of the first tunneling barrier and the energy bandbending is adjusted by controlling interface charges, interface dipoles,and formation of SAMs (self-assembled monolayers) at a surface of thefirst tunneling barrier. The electron energy filter can also be formedfrom a sequential arrangement of the second electrode, an additionalfirst tunneling barrier and an additional second tunneling barrier. Insuch a case, the quantum well is formed in the additional firsttunneling barrier and a discrete quantum state or multiple number ofdiscrete quantum states are formed in the quantum well. The depth of thequantum well is controlled by energy band bending of the additionalfirst tunneling barrier and the energy band bending is adjusted bycontrolling interface charges, interface dipoles, and formation of SAMs(self-assembled monolayers) at a surface of the additional firsttunneling barrier.

FIGS. 30A-30J show a schematic (not to scale) of process flow for afabrication of the energy-filtered cold electron transistor shown inFIG. 29. Here the materials for the substrate, isolation layer, centralisland, electrode, first tunneling barrier, and second tunneling barrierare displayed. The materials displayed are to show an example ofmaterials selection and other sets of materials can be used. In thisexample, Si, SiO₂, Si, Cr, Cr₂O₃ and SiO₂ are used for substrate,isolation layer, central island, electrode, first tunneling barrier, andsecond tunneling barrier, respectively.

FIG. 30A shows a starting structure, in which Si layer (for the centralisland) is separated from the substrate with SiO₂ isolation layer. Ontop of the Si layer, a SiO₂ layer is deposited as shown in FIG. 30B. Aresist is deposited on the SiO₂ layer and patterned using lithography asshown in FIG. 30C. Using the resist, the underlying SiO₂/Si layers arevertically etched using plasma etching (reactive ion etching: RIE) asshown in FIG. 30D. The resist is removed as shown in FIG. 30E. Thesidewall of the Si central island is oxidized producing SiO₂ layer,which serves as the second tunneling barrier, as shown in FIG. 30F.Alternatively, the second tunneling barrier can be formed usingdeposition techniques such as plasma enhanced chemical vapor deposition(PECVD), atomic layer deposition (ALD), or sputtering. Then, the firsttunneling barrier (Cr₂O₃) is conformally deposited using techniques suchas sputtering as shown in FIG. 30G. The metal electrode (Cr) isdeposited using techniques such as e-beam evaporation or thermalevaporation as shown in FIG. 30H. The structures positioned above the Sicentral island are then lifted off by removing SiO₂ using HF etching andsonication, leaving a planer structure, as shown FIG. 30I. The gatedielectric and gate electrode are formed using lithography anddeposition of gate dielectric and gate metal, completing theenergy-filtered cold electron transistor structure, as shown in FIG.30J.

More specifically, the method for forming an energy-filtered coldelectron transistor includes providing a substrate, forming ordepositing an isolation layer on the substrate, forming or depositing asemiconductor material or a metal on the isolation layer in FIG. 30A.The semiconductor material or the metal is used to from the centralisland and can be selected from the group including Si, Ge, CdSe, CdTe,GaAs, InP, InAs, Al, Pb, Cr, Cu, Au, Ag, Pt, Pd, and Ti. An organicmaterial, an inorganic material, a magnetic material or asuperconducting material can also be used as a central island material.Forming or depositing a sacrificial material on the central islandmaterial in FIG. 30B. Depositing and patterning a resist to define ashape of the central island in FIG. 30C. Forming the central island byetching or removing the sacrificial material and the semiconductormaterial or the metal around the central island in FIG. 30D, andremoving the resist in FIG. 30E. A second tunneling barrier material isformed or deposited around the semiconductor material or the metal ofthe central island in FIG. 30F. The second tunneling barrier materialforms a second tunneling barrier on a first side of the central islandand an additional second tunneling barrier on a second side of thecentral island. A first tunneling barrier material is formed ordeposited on top and around the sacrificial material on the centralisland, on the second tunneling barrier, and on the isolation layer inFIG. 30G. The first tunneling barrier material forms a first tunnelingbarrier adjacent to the second tunneling barrier and an additional firsttunneling barrier adjacent to the additional second tunneling barrier.The first tunneling barrier and the second tunneling barrier can be asingle type of material, or two different materials. For example, thefirst tunneling barrier can be selected from the group including Al₂O₃,Cr₂O₃, and TiO_(x) and the second tunneling barrier can be selected fromthe group including SiO₂, Si₃N₄, Al₂O₃, Cr₂O₃, and TiO_(x). An electrodematerial is formed or deposited on the first tunneling barrier to form afirst electrode adjacent to the first tunneling barrier and a secondelectrode adjacent to the additional first tunneling barrier in FIG.30H. The electrode material for first electrode and second electrode canbe selected from the group including Al, Pb, Cr, Cu, Au, Ag, Pt, Pd, andTi. All materials above a plane substantially level with a top of thefirst electrode and the second electrode are removed or lifted off inFIG. 30I. A gate dielectric is formed or deposited above a portion ofthe first electrode, the first tunneling barrier, the second tunnelingbarrier, the central island, the additional second tunneling barrier,the additional first tunneling barrier and a portion of the secondelectrode in FIG. 30J. Alternatively, the gate dielectric is formed ordeposited only above the central island. A gate electrode is formed ordeposited on the gate dielectric in FIG. 30J. In addition, one or morevias and metal interconnects attached to the first electrode, the secondelectrode, the gate electrode or a combination thereof can be formed(not shown).

FIGS. 31A-31B show cross sectional and top views (not to scale) of theenergy-filtered cold electron transistor in accordance with the presentinvention. The gate electrode and gate dielectric are not shown forsimplicity. The dotted line in FIG. 31B indicates where the crosssection is made for the cross sectional view in FIG. 31A. FIGS. 32A-32Eshow schematic of the mask set (not to scale) that can be used tofabricate the transistor structure with the procedure in FIGS. 30A-30J.The central island is formed using a first mask in a first patternsubstantially as shown in FIG. 32A. The first electrode and the secondelectrode are formed using a second mask in a second patternsubstantially as shown in FIG. 32B. The gate electrode is formed using athird mask in a third pattern substantially as shown in FIG. 32C. Theone or more vias are formed using a fourth mask in a fourth patternsubstantially as shown in FIG. 32D. The one or more metal interconnectsare formed using a fifth mask in a fifth pattern substantially as shownin FIG. 32E.

The energy-filtered cold electron transistor in FIGS. 29-31 can befabricated with completely CMOS-compatible processes and materials. Theenergy-filtered cold electron transistors can be fabricated on a largescale in parallel processing using CMOS-compatible mask steps.

It will be understood by those of skill in the art that information andsignals may be represented using any of a variety of differenttechnologies and techniques (e.g., data, instructions, commands,information, signals, bits, symbols, and chips may be represented byvoltages, currents, electromagnetic waves, magnetic fields or particles,optical fields or particles, or any combination thereof). Likewise, thevarious illustrative logical blocks, modules, circuits, and algorithmsteps described herein may be implemented as electronic hardware,computer software, or combinations of both, depending on the applicationand functionality. Moreover, the various logical blocks, modules, andcircuits described herein may be implemented or performed with a generalpurpose processor (e.g., microprocessor, conventional processor,controller, microcontroller, state machine or combination of computingdevices), a digital signal processor (“DSP”), an application specificintegrated circuit (“ASIC”), a field programmable gate array (“FPGA”) orother programmable logic device, discrete gate or transistor logic,discrete hardware components, or any combination thereof designed toperform the functions described herein. Similarly, steps of a method orprocess described herein may be embodied directly in hardware, in asoftware module executed by a processor, or in a combination of the two.A software module may reside in RAM memory, flash memory, ROM memory,EPROM memory, EEPROM memory, registers, hard disk, a removable disk, aCD-ROM, or any other form of storage medium known in the art. Althoughpreferred embodiments of the present invention have been described indetail, it will be understood by those skilled in the art that variousmodifications can be made therein without departing from the spirit andscope of the invention as set forth in the appended claims.

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The invention claimed is:
 1. An energy-filtered cold electron nanopillar device comprising: a first electrode disposed on an isolation layer; a first tunneling barrier disposed on the first electrode; a second tunneling barrier disposed on the first tunneling barrier; an island material comprised of a semiconductor or metal disposed on the second tunneling barrier; an additional second tunneling barrier disposed on the island material; an additional first tunneling barrier disposed on the additional second tunneling barrier; and a second electrode disposed on the additional first tunneling barrier; wherein the first electrode, the first tunneling barrier, the second tunneling barrier, the island material, the additional second tunneling barrier, the additional first tunneling barrier and the second electrode form a nanopillar; wherein quantum wells or quantum dots are formed in the first tunneling barrier and/or the additional first tunneling barrier; and wherein discrete energy levels are formed in the quantum wells or quantum dots.
 2. The device as recited in claim 1, wherein the first tunneling barrier is spontaneously formed or deposited on the first electrode, and the additional first tunneling barrier is spontaneously formed or deposited on the additional second tunneling barrier.
 3. The device as recited in claim 1, wherein the device exhibits electron energy filtering through the discrete energy levels of the quantum wells or quantum dots.
 4. The device as recited in claim 3, wherein the device exhibits lowering of electron temperature through the electron energy filtering.
 5. The device as recited in claim 4, wherein the device has an effective electron temperature of less than or equal to 45 K at room temperature without any external cooling.
 6. The device as recited in claim 1, further comprising a source pad disposed on the isolation layer in contact with the first electrode.
 7. The device as recited in claim 1, further comprising: a passivation material disposed around the nanopillar; a drain pad disposed on the passivation material in contact with the second electrode; and one or more vias and metal interconnects attached to the source pad, the drain pad or both pads.
 8. The device as recited in claim 6, further comprising: an insulating material disposed on the source pad and around the nanopillar; a gate electrode disposed within the insulating material and separated from the nanopillar; a drain pad in contact with the second electrode and a gate pad in contact with the gate electrode; and a passivation layer over the resulting structure.
 9. The device as recited in claim 8, further comprising one or more vias and metal interconnects attached to the source pad, the drain pad, the gate pad or a combination thereof.
 10. A method for fabricating an energy-filtered cold electron nanopillar device comprising the steps of: depositing a first electrode on an isolation layer; depositing or spontaneously forming a first tunneling barrier on the first electrode; depositing a second tunneling barrier on the first tunneling barrier; depositing an island material on the second tunneling barrier; depositing an additional second tunneling barrier on the island material; depositing or spontaneously forming an additional first tunneling barrier on the additional second tunneling barrier; depositing a second electrode on the additional first tunneling barrier; and producing a nanopillar from the first electrode, the first tunneling barrier, the second tunneling barrier, the island material, the additional second tunneling barrier, the additional first tunneling barrier, and the second electrode.
 11. The method as recited in claim 10, wherein the device exhibits electron energy filtering through discrete energy levels of quantum wells or quantum dots formed in the first tunneling barrier and/or the additional first tunneling barrier.
 12. The method as recited in claim 11, wherein the device exhibits lowering of electron temperature through the electron energy filtering.
 13. The method as recited in claim 10, wherein the device has an effective electron temperature of less than or equal to 45 K at room temperature without any external cooling.
 14. The method as recited in claim 11, wherein the device exhibits band bending of the first tunneling barrier and/or the additional first tunneling barrier through formation of interface dipoles, interface charges, formation of self-assembled monolayers, UV-ozone treatment, plasma treatment, or a combination thereof.
 15. The method as recited in claim 12, wherein the device has a low an effective electron temperature of less than or equal to 45 K and an electric current turn-on and turn-off capability with a steepness of less than or equal to 10 mV/decade at room temperature.
 16. The method as recited in claim 10, further comprising the step of disposing a gate electrode that surrounds the nanopillar producing an energy-filtered cold electron nanopillar transistor.
 17. The method as recited in claim 16, the device having a subthreshold swing of less than or equal to 10 mV/decade at room temperature.
 18. The method as recited in claim 10, the device having a supply voltage of less than or equal to 0.1V.
 19. The method as recited in claim 10, wherein the first tunneling barrier and the additional first tunneling barrier comprise a single type of material or two different materials.
 20. The method as recited in claim 10, wherein the second tunneling barrier and the additional second tunneling barrier comprise a single type of material or two different materials.
 21. The method as recited in claim 10, wherein the first electrode comprises a Cr source electrode, the first tunneling barrier and the additional first tunneling barrier comprise Cr₂O₃, the second tunneling barrier and the additional second tunneling barrier comprise SiO₂ or Si₃N₄, the island material comprises Si, and the second electrode comprises a Cr drain electrode.
 22. The method as recited in claim 10, wherein: the first electrode and second electrode are formed from a material selected from the group consisting of Al, Pb, Cr, Cu, Au, Ag, Pt, Pd, and Ti; the first tunneling barrier and the additional first tunneling barrier are formed from a material selected from the group consisting of Al₂O₃, Cr₂O₃, and TiO_(x); the second tunneling barrier and the additional second tunneling barrier are formed from a material selected from the group consisting of SiO₂, Si₃N₄, Al₂O₃, Cr₂O₃, and TiO_(x); and the island material is selected from the group consisting of Si, Ge, CdSe, CdTe, GaAs, InP, InAs, Al, Pb, Cr, Cu, Au, Ag, Pt, Pd, and Ti.
 23. The method as recited in claim 10, wherein the nanopillar is produced using a vertical etching process or a liftoff process. 